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nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use document id: pmc- pmc-2010850, issue 1 PM8621 nse-8g 8g narrowband switch element data sheet preliminary issue 1: may, 2001
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 1 document id: pmc-2010850, issue 1 legal information copyright ? 2001 pmc-sierra, inc. the information is proprietary and confidential to pmc-sierra, inc., and for its customers? internal use. in any event, you cannot reproduce any part of this document, in any form, without the express written consent of pmc-sierra, inc. pmc-2010850, (p1) disclaimer none of the information contained in this document constitutes an express or implied warranty by pmc-sierra, inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of pmc-sierra, inc., or any portion thereof, referred to in this document. pmc-sierra, inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. in no event will pmc-sierra, inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not pmc-sierra, inc. has been advised of the possibility of such damage. trademarks s/uni is a registered trademark of pmc-sierra, inc. and nse-8g, sbs, chess, temux-84, aal1gator-32, spectra, freedm-336, and sbi are trademarks of pmc-sierra, inc.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 2 document id: pmc-2010850, issue 1 contacting pmc-sierra pmc-sierra 8555 baxter place burnaby, bc canada v5a 4v7 tel: (604) 415-6000 fax: (604) 415-6200 document information: document@pmc-sierra.com corporate information: info@pmc-sierra.com technical support: apps@pmc-sierra.com web site: http://www.pmc-sierra.com
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 3 document id: pmc-2010850, issue 1 table of contents 1 features..................................................................................................................... 1 1 2 applications ...............................................................................................................12 3 references ................................................................................................................13 4 application examples ................................................................................................14 5 block diagram ...........................................................................................................17 6 description.................................................................................................................19 7 pin diagram ...............................................................................................................20 8 pin description...........................................................................................................24 8.1 pin description table ........................................................................................24 8.2 analog power filtering recommendations.......................................................38 9 functional description ...............................................................................................40 9.1 lvds overview .................................................................................................40 9.1.1 lvds receiver (rxlv) ........................................................................41 9.1.2 lvds transmitter (txlv).....................................................................41 9.1.3 lvds transmit reference (txref) ....................................................41 9.1.4 data recovery unit (dru) ...................................................................42 9.1.5 parallel to serial converter (piso) ......................................................42 9.1.6 clock synthesis unit (csu) .................................................................42 9.2 receive 8b/10b frame aligner (r8td) ............................................................42 9.2.1 fifo buffer...........................................................................................42 9.3 transmit 8b/10b encoder (t8te).....................................................................43 9.3.1 sbi336s 8b/10b character encoding .................................................43 9.3.2 serial telecombus 8b/10b character encoding..................................44 9.3.3 serial sbi336s and telecombus alignment ........................................46 9.3.4 character alignment block...................................................................46 9.3.5 frame alignment ..................................................................................47 9.3.6 sbi336s multiframe alignment ............................................................49 9.4 ds0 cross bar switch (dcb) ............................................................................49 9.5 clock synthesis and transmit reference digital wrapper (cstr)..................50 9.6 fabric latency...................................................................................................50 9.7 jtag support....................................................................................................50 9.8 microprocessor interface ..................................................................................50 9.9 in-band link controller (ilc).............................................................................51
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 4 document id: pmc-2010850, issue 1 9.9.1 in-band signaling channel fixed overhead........................................52 9.10 microprocessor interface ..................................................................................53 10 normal mode register description............................................................................57 11 test features description........................................................................................125 11.1 master test and test configuration registers ................................................125 11.2 jtag test port ................................................................................................127 11.2.1 boundary scan cells..........................................................................131 12 operation .................................................................................................................134 12.1 software default settings ...............................................................................134 12.1.1 setting the t8te time-slot configuration #1 register.......................134 12.1.2 setting the t8te time-slot configuration #2 register.......................134 12.1.3 configuring the nse-8g to use fewer links ....................................134 12.1.4 pcb design notes .............................................................................136 12.2 ?c1? synchronization.......................................................................................136 12.3 synchronized control setting changes ..........................................................137 12.3.1 sbs/nse-8g systems with ds0 and cas switching .......................137 12.3.2 sbs/nse-8g systems switching ds0s without cas........................139 12.3.3 sbs/nse-8g non-ds0 level switching with sbi336 devices ..........141 12.4 nse-8g cpu interaction with the switching cycle when using the ilc.......142 12.5 controlling frame alignment in the receive port ...........................................143 12.6 ds0 cross-bar switch (dcb) operation ........................................................144 12.6.1 configuring the dcb using port transfer mode.................................144 12.6.2 configuring the dcb using word transfer mode:...............................145 12.6.3 reading configurations......................................................................146 12.6.4 dcb online to offline memory page copy ........................................146 12.7 telecombus mode operation ..........................................................................147 12.8 sbi column mode operation ..........................................................................147 12.9 sbi ds0 mode operation ...............................................................................148 12.10 sbi ds0 with cas mode operation................................................................148 12.11 ilc operation..................................................................................................149 12.12 ilc cpu operations .......................................................................................149 12.12.1 accessing the transmit message fifo .............................................149 12.12.2 accessing the receive message fifo ..............................................150 12.12.3 handling the transmit header ...........................................................153 12.12.4 handling the receive header ............................................................154
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 5 document id: pmc-2010850, issue 1 12.12.5 handling interrupts .............................................................................154 12.12.6 bypass function.................................................................................154 12.13 switch setting algorithm .................................................................................156 12.13.1 problem description ...........................................................................156 12.13.2 na?ve algorithm ..................................................................................157 12.13.3 bi-partite graphs .................................................................................159 12.13.4 unicast ...............................................................................................160 12.13.5 experimental results .........................................................................162 12.13.6 multicast .............................................................................................162 12.14 jtag support..................................................................................................163 12.14.1 tap controller ....................................................................................164 12.14.2 states..................................................................................................164 12.14.3 instructions .........................................................................................166 13 functional timing.....................................................................................................167 13.1 receive interface timing ................................................................................167 13.2 transmit interface timing................................................................................168 14 absolute maximum ratings.....................................................................................170 15 d.c. characteristics.................................................................................................171 16 microprocessor interface timing characteristics ....................................................173 17 a.c. timing characteristics .....................................................................................176 17.1 input timing.....................................................................................................176 1.1 reset timing ...................................................................................................177 17.2 serial sbi bus interface..................................................................................178 17.3 jtag port interface.........................................................................................178 18 ordering and thermal information ..........................................................................180 18.1 packaging information ....................................................................................180 18.2 thermal information ........................................................................................180 19 mechanical information ...........................................................................................182 notes .......................................................................................................................... .....183
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 6 document id: pmc-2010850, issue 1 list of registers register 000h: nse-8g master reset..............................................................................58 register 001h: nse-8g individual channel reset...........................................................59 register 002h: nse-8g master jtag id .........................................................................60 register 003h: sbs page select ? page 0 .......................................................................61 register 004h: sbs page select ? page 1 .......................................................................62 register 005h: nse-8g master interrupt source .............................................................63 register 006h: nse-8g master ilc interrupt source ......................................................65 register 007h: nse-8g master r8td interrupt source...................................................66 register 008h: nse-8g master t8te interrupt source ...................................................67 register 009h: nse-8g master clock monitor .................................................................68 register 00ah: nse-8g dcb cmp select........................................................................69 register 00bh: nse-8g interrupt enable register ..........................................................70 register 00ch: nse-8g subsystem interrupt enable register .......................................71 register 00dh: nse-8g r8td tip register .....................................................................72 register 00eh: sbs user bit 0 .........................................................................................73 register 00fh: sbs user bit 1 .........................................................................................74 register 010h: sbs user bit 2 .........................................................................................75 register 011h: nse-8g free user register...................................................................76 register 012h: correct r8td_rx_c1 pulse monitor ......................................................77 register 013h: unexpected r8td_rx_c1 interrupt........................................................78 register 014h: missing r8td_rx_c1 interrupt...............................................................79 register 015h: unexpected r8td_rx_c1 interrupt enable ...........................................80 register 016h: missing r8td_rx_c1 interrupt enable ..................................................81 register 020h, 024h: cstr #1 ? 2 control*....................................................................82 register 021h, 025h: cstr #1 ? 2* interrupt enable and csu lock status ..................83 register 022h, 026h: cstr #1 ? 2* interrupt indication..................................................84 register 044h: dcb configuration port 11-6 register......................................................85 register 045h: dcb configuration port 5-0 register .......................................................86 register 046h: dcb configuration output register. ........................................................87 register 047h: dcb access mode register .....................................................................88 register 048h: dcb c1 delay (rc1dly) register. ..........................................................91 register 04ah: dcb frame size register ........................................................................92 register 04ch: dcb configuration register ....................................................................93
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 7 document id: pmc-2010850, issue 1 register 04dh: dcb interrupt status register. .................................................................96 register 100h + n*20h, r8td control and status...........................................................97 register 101h + n*20h, r8td interrupt status................................................................99 register 102h + n*20h, r8td line code violation count ............................................101 register 103h + n*20h, rxlv and dru control ...........................................................102 register 108h + n*20h, t8te control and status .........................................................104 register 109h + n*20h, t8te interrupt status ..............................................................106 register 10ah + n*20h: t8te time-slot configuration #1 ............................................107 register 10bh + n*20h: t8te time-slot configuration #2 ............................................108 register 10ch + n*20h, t8te test pattern ...................................................................109 register 10dh + n*20h, txlv and piso control .......................................................... 110 register 110h + n*20h, ilc transmit fifo data........................................................... 111 register 111h + n*20h, ilc transmit control register ................................................. 112 register 112h + n*20h, ilc transmit misc.status and fifo synch register................ 113 register 113h + n*20h, ilc receive fifo data register.............................................. 115 register 114h + n*20h, ilc receive control register................................................... 116 register 115h + n*20h, ilc receive auxiliary, status and fifo synch register.......... 117 register 116h + n*20h, ilc interrupt enable and control register ...............................121 register 117h + n*20h: ilc interrupt reason register..................................................124 register 800h: nse-8g master test ..............................................................................126
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 8 document id: pmc-2010850, issue 1 list of figures figure 1 an oc-48 t1/e1 adm (individually drop/add any t1/e1 in sts-48) ..............14 figure 2 an oc-48 t1/e1 adm (drop/add up to sts-48 at sts-1 granularity)............14 figure 3 any-service-any-port tdm access solution ....................................................15 figure 4 any-service-any-port ds0-granularity phy card ...........................................16 figure 5 nse- 8g block diagram showing functional blocks .......................................17 figure 6 nse-8g ubga-480 ball diagram (bottom-view).............................................20 figure 7 analog power filter circuit................................................................................39 figure 8 generic lvds link block diagram ...................................................................40 figure 9 character alignment state machine .................................................................47 figure 10 frame alignment state machine.....................................................................48 figure 11 in-band signaling channel message format .................................................52 figure 12 in-band signaling channel header format ....................................................52 figure 13 input observation cell (in_cell) ................................................................131 figure 14 output cell (out_cell) ..............................................................................132 figure 15 bidirectional cell (io_cell) .........................................................................132 figure 16 layout of output enable and bidirectional cells...........................................133 figure 17 shutting down a link ....................................................................................135 figure 18 ?c1? synchronization control ........................................................................137 figure 19 temux-84?/sbs/nse/sbs/aal1gator-32? system ds0 switching with cas .......................................................................................................138 figure 20 cas multiframe timing .................................................................................139 figure 21 switch timing dsos with cas .....................................................................139 figure 22 temux-84/sbs/nse/sbs/freedm-336 system ds0 switch no cas...............................................................................................................140 figure 23 switch timing - dsos without cas ..............................................................141 figure 24 non ds0 switch timing ................................................................................142 figure 25 architecture of the ram input interface........................................................144 figure 26 c1 position in the first row..........................................................................149 figure 27 transport overhead affected by ilc ............................................................155 figure 28 example graph .............................................................................................158 figure 29 time:space:time switching in one nse-8g and four single-ported sbss .............................................................................................................158 figure 30 example graph .............................................................................................160 figure 31 example problem..........................................................................................161
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 9 document id: pmc-2010850, issue 1 figure 32 merged graph ...............................................................................................161 figure 33 relabeled graph ...........................................................................................162 figure 34 boundary scan architecture .........................................................................163 figure 35 tap controller finite state machine.............................................................164 figure 36 receive interface timing ..............................................................................167 figure 37 transmit interface timing .............................................................................168 figure 38 cmp timing ..................................................................................................169 figure 39 microprocessor interface read timing .........................................................173 figure 40 microprocessor interface write timing .........................................................175 figure 41 nse-8g input timing ....................................................................................176 figure 42 rstb timing.................................................................................................177 figure 43 jtag port interface timing...........................................................................179
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 10 document id: pmc-2010850, issue 1 list of tables table 1 analog power filters ..........................................................................................39 table 2 sbi336s character encoding ............................................................................43 table 3 serial telecombus character encoding ............................................................45 table 4 switching control ram layout...........................................................................50 table 5 in-band message header fields ........................................................................52 table 6 nse-8g register map........................................................................................54 table 7 tx fifo message level ..................................................................................114 table 8 rx fifo message level ..................................................................................119 table 9 rxfifo threshold values ...............................................................................122 table 10 rxfifo timeout delay ..................................................................................123 table 11 test mode register memory map ..................................................................125 table 12 instruction register (length - 3 bits) ..............................................................127 table 13 identification register.....................................................................................127 table 14 boundary scan register ................................................................................128 table 15 absolute maximum ratings............................................................................170 table 16 d.c characteristics ........................................................................................171 table 17 microprocessor interface read access .........................................................173 table 18 microprocessor interface write access..........................................................175 table 19 nse-8g input timing (figure 40) ..................................................................176 table 20 rstb timing (figure 41 ) ..............................................................................177 table 21 serial sbi bus interface .................................................................................178 table 22 jtag port interface ( figure 42) ....................................................................178
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 11 document id: pmc-2010850, issue 1 1 features the narrowband switch element 8g (nse-8g): ? implements a scaleable bandwidth interconnect (sbi?) ds0 granularity space switch. ? implements a sonet/sdh vt1.5/vt2/tu11/tu12 granularity space switch for the serial 777.6 mhz lvds telecombus. ? with an allied pm8610 sbs or pm8611 sbs-lite device, implements a ds0 granularity memory-space-memory switch. ? supports 12 sts-12 equivalent serial ports via 777.6 mhz, 8b/10b encoded lvds links (each port can be either serial telecombus or serial sbi336s) ? when configured for sbi mode, switches ds0 or n*ds0 for all t1 and e1 tributaries and aggregate columns for switching t1, e1, tvt1.5, tvt2, ds3 and e3 tributaries. ? when configured for the serial 777.6 mhz telecombus interface, switches any sonet/sdh virtual tributary (vt) or tributary unit (tu) up to sts-1. ? supports switching of arbitrary non-standard octet aggregates. ? supports unicast, multicast, and broadcast for all switching modes. ? provides 8 gbit/s (96,768 ds0s, 4.032 t1s/vt1.5s, 3,024 e1s/vt2s, 144 ds3s/e3s) switching. ? works with sbs devices that support up to four 19.44 mhz sbi or one 77.76 mhz sbi336 bus that communicates with pmc-sierra?s sbi device family. alternatively, the sbs and sbs-lite devices support up to four 19.44 mhz sts-3 telecombuses or one 77.76 mhz sts- 12 telecombus for connection with pmc-sierra?s spectra family of devices. ? can be combined in applications with pmc-sierra?s chess? chip set devices (pm5374 tse and pm5307 tbs). ? supports a microprocessor interface used to configure/control the nse and make ds0- granularity switch settings. ? supports clean error checked 8 mbit/s full-duplex, in-band communications channels from its attached microprocessor to the attached microprocessors of each of the 12 attached sbs336s devices. this channel is used to initialize and control the sbss, or other such devices, and to implement call-establishment set-up changes. ? supports jtag for all non-lvds signals. ? requires dual power supplies at 1.8v and 3.3v. ? packaged as a 480 ball ubga. ? in conjunction with the sbs or sbs-lite, supports ?1+1? and ?1:n? fabric redundancy.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 12 document id: pmc-2010850, issue 1 2 applications the PM8621 narrowband switch element 8g (nse-8g) supports a variety of flexible layer 1/layer 2 architectures in combination with the following pmc-sierra devices: ? pm8610 sbs and pm8611 sbs-lite (sbi serializer and memory switching stage). ? sbi bus devices (temux?/temap, freedm devices, s/uni?-ima devices, aal1gator? devices and other future devices). ? chess? chip set devices (pm5374 tse, pm5307 tbs, pm5315 spectra?-2488, and pm7390 s/uni?-mach48). these architectures include: ? t1/e1 sonet adms. ? tdm asap applications. ? phy cards with ds0 (and above) level switching. ? pstn replacement switching cores, as part of any-service-any-port applications, and ? voice gateways.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 13 document id: pmc-2010850, issue 1 3 references 1. ansi - t1.105-1995, ?synchronous optical network (sonet) ? basic description including multiplex structure, rates, and formats?, 1995. 2. telcordia - sonet transport systems: common generic criteria, gr-253-core, issue 2, revision 2, january 1999. 3. itu, recommendation g.707 - "digital transmission systems ? terminal equipments - general", march 1996. 4. ieee 802.3, ?carrier sense multiple access with collision detection (csma/cd) access method and physical layer specifications?, section 36.2, 1998. 5. a.x. widmer and p.a. franaszek, ?a dc-balanced, partitioned-block, 8b/10b transmission code,? ibm journal of research and development, vol. 27, no 5, september 1983, pp 440- 451. 6. u.s. patent no. 4,486,739, p.a. franaszek and a.x. widmer, ?byte oriented dc balanced (0,4) 8b/10b partitioned block transmission code,? december 4, 1984. 7. ieee std 1596.3-1996, ?ieee standard for low-voltage differential signals (lvds) for scalable coherent interface (sci)?, approved march 21, 1996 8. l.r. ford, d.r. fulkerson, ?flows in networks'', maximum cardinality matchings in bipartite graphs
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 14 document id: pmc-2010850, issue 1 4 application examples figure 1 illustrates an oc-48 sonet ring add/drop multiplexer. the pm5363 tupp-622 devices align all paths to transport frames in preparation for vt1.5/vt2 granularity switching. the pm8610 sbi336 bus serializer (sbs?) an PM8621 narrowband switching element 8g (nse-8g?) devices support vt1.5/vt2 and above switching. the add and drop buses are provided by the sbss that are not in the sonet ring path. in this case, they connect to t1 and e1 mapper ports. figure 1 an oc-48 t1/e1 adm (individually drop/add any t1/e1 in sts-48) spectra- 2488 4 x tupp- 622 4 x sbs nse20g 4 x sbs 4 x tupp- 622 spectra- 2488 sbs 4 x temap -84 4 x octal -liu ** ** 42 required to terminate links for all 4 temaps figure 2 illustrates another oc-48 sonet ring adm. in this application, the network of three pm5310 telecombus serializers (tbss) from pmc-sierra?s chess? chip set add, drop, and groom traffic at sts-1 granularities. the four tupp-622 devices align any dropped sts-1s (paths to transport frames). the virtual tributary (vt) or tributary unit (tu) switching solution is provided by the sbs-nse-8g-sbs network below the tupp-622s. four sbss support up to an sts-48 amount of add/drop traffic. figure 2 an oc-48 t1/e1 adm (drop/add up to sts-48 at sts-1 granularity) specta- 2488 4 x sbs 4 x tupp- 622 specta- 2488 tbs tbs tbs nse8g sbs sbs sbs sbs sbi device sbi device sbi device sbi device sbi device sbi device sbi device sbi device sbi device sbi device sbi device sbi device sbi device sbi device sbi device sbi device
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 15 document id: pmc-2010850, issue 1 figure 3 illustrates the organization of the access line size card(s) from a sonet any service any port (asap) product. all traffic from the nse-8g to the sbi link layer devices is path- aligned. see figure 4 for a description of the phy line cards compatible with the system in figure 3. figure 3 any-service-any-port tdm access solution sbs freedm- 336 sbs sbs sbs- lite 4 x ima-84 12 x aal1gator- 32 4 x temux-84 dsp processors h-mvip nse8g any-phy (packet) any-phy (cell) any-phy (cell) t1/e1/ds0/n*ds0 layer 2 processing figure 4 shows the organization of a sonet phy card compatible with figure 3. as shown, both figure 3 and figure 4 have nse-8gs, but only one instance of this device is required to connect all the sbss. a likely packaging of this combined system would place the nse-8g (and a standby nse-8g) on separate fabric cards. in figure 4, pm8315 temuxs align paths to transport frames. note: figure 3 assumes this alignment.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 16 document id: pmc-2010850, issue 1 figure 4 any-service-any-port ds0-granularity phy card sbs sbs sbs sbs 4 x temux-84 nse8g sonet/t1/e1 termination - vt/tu/ds0 switching 4 x temux-84 4 x temux-84 4 x temux-84 tbs tbs tbs tbs tbs spectra- 2488
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 17 document id: pmc-2010850, issue 1 5 block diagram the nse-8g is organized as a ds0 granularity space switch. alternatively, the nse-8g is organized as a self aligning (with respect to sts-12 boundaries in telecombus mode) vt1.5/vt2 granularity space switch. figure 5 nse- 8g block diagram showing functional blocks clock synthesis unit tx ref microprocessor interface a[11:0] d[31:0] rstb csb wrb rdb ale intb jtag trstb tck tms tdi tdo lvds receiver (rxlv) data recovery unit (dru) receive 8b/10b decoder (r8td) rp[0] rn[0] 1/2 in-band link controller (ilc) tp[0] tn[0] lvds transmitt er (txlv) transmit serializer (piso) transmit 8b/10b encoder (t8te) 1/2 in-band link controller (ilc) lvds receiver (rxlv) data recovery unit (dru) receive 8b/10b decoder (r8td) rp[1] rn[1] 1/2 in-band link controller (ilc) tp[1] tn[1] transmit 8b/10b encoder (t8te) 1/2 in-band link controller (ilc) lvds receiver (rxlv) data recovery unit (dru) receive 8b/10b decoder (r8td) rp[11] rn[11] 1/2 in-band link controller (ilc) tp[11] tn[11] transmit 8b/10b encoder (t8te) 1/2 in-band link controller (ilc) lvds transmitt er (txlv) lvds transmitt er (txlv) transmit serializer (piso) transmit serializer (piso) ds0 crossbar switch (dcb) rc1fp cmp sysclk the r8td, in combination with the rxlv and dru receive, decode and align incoming sbi336/sts-12-equivalent lvds links. outputs are provided to the primary switching flow and to the in-band signaling channel. these provide all analog and digital functions to terminate a full-duplex 777.6 mhz serial sbi336s or 777.6 mhz serial telecombus on lvds. a 12 x 12 ds0 crossbar switch(dcb) stage switches data and control signals between the 12 ports. the switching instructions are stored in two pages of ram configured as offline and online allowing the user to modify the offline page.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 18 document id: pmc-2010850, issue 1 the t8te, in combination with the piso and txlv perform 8b/10b coding and emits the lvds bit streams. these provide all analog and digital functions to launch a full-duplex 777.6 mhz serial sbi336s bus or 777.6 mhz serial telecombus on lvds. the microprocessor bus interface and in-band signaling units (ilc) provide a clean (error checked) channel between the nse-8g and sbss. this can be used to send messages between the nse-8g microprocessor-and the sbs microprocessors in a user defined format.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 19 document id: pmc-2010850, issue 1 6 description the PM8621 nse-8g is a monolithic cmos integrated circuit packaged in a 480 ball ubga that performs ds0 and above granularity space switching on 12 sbi336 streams carried as serial sbi336s in 8b/10b coding over lvds at 777.6 mbit/s. the nse-8g also performs vt1.5/vt2 and above granularity switching on 12 sts-12/stm-4 sonet/sdh streams, carried as serial telecombus signals in 8b/10b coding over lvds at 777.6 mbit/s. the nse-8g is typically used with up to 12 pm8610 sbs or pm8611 sbs-lite devices to provide memory-space-memory switching systems. as each sbs supports either four sbi buses at 19.44 mhz or one sbi336 bus at 77.76 mhz, the overall system supports any mixture of sbi and sbi336 byte serial buses, ranging from 48 19.44 mhz sbi buses to 12 sbi336 77.76 mhz buses that do not exceed an aggregate bandwidth of sts-144, or about 7.5 gbit/s. in telecombus mode, the sbs devices support the same range of flexibility for 48 19.44 mhz and 12 77.76 mhz telecombuses at vt1.5/vt2 granularity central to the nse-8g is a 12 x 12 cross bar switch. every clock cycle, the cross bar switches a byte of data with control signals from each input port to an output port. the byte of data may be a ds0 channel from a t1/e1 or may be one byte of a column comprising a t1, e1, ds3, e3, vt1.5, vt2 or sts-1. in order for switching to take place, all input and output streams must be synchronized. this is done via the rc1fp input signal. when switching t1s, e1s, vts and other higher order units, only sbi336 multiframe alignment is required. the same applies for telecombus mode where only frame alignment is required. an in-band control link over the serial lvds interface allows the nse-8g to communicate with the microprocessors attached to the sbs, sbs-lite or other serial sbi336s devices. the effective bandwidth of each inband link to each device is 8 mbit/s. the inband link provides error detection on 32 byte user messages and some near realtime control signals between devices. using the near realtime control signals the nse-8g is able to synchronize page switching, indicate switchover between working or protected links and exchange three user defined signals (software) and eight auxilliary signals (software). the user and auxilliary signals can be used to indicates things like interrupts or can be used for handshaking between the end point microprocessors. the message format is left to the user of the devices. the only constraint is that each message is a maximum of 32 bytes long.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 20 document id: pmc-2010850, issue 1 7 pin diagram the nse-8g is packaged in a 35 mm x 35 mm 480 ball ubga. figure 6 nse-8g ubga-480 ball diagram (bottom-view) upper left 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a vss vss vss vss vddo vss nc vss nc vss reserved vss reserved vss reserved vss vddi b vss avdh vddo vddo vddo vddi nc nc nc vddi reserved reserved reserved reserved reserved reserved rstb c vss avdh avdh vddo vddi reserved nc nc vddi nc reserved vddi reserved reserved reserved reserved vddi d vss avdh avdh avdh vddo reserved vddi vddo nc nc reserved vddo reserved reserved reserved vddo vddi e resk1 res1 nc nc f vss nc nc avdl1 gncncncnc h vss nc nc avdh jncncncnc k vss nc nc vddi lncncncnc m vss nc nc avdh n vddi avdl2 nc nc p vss nc nc vddi rncncncnc t nc nc avdl4 avdl3 u nc nc avdl5 csu_av dh
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 21 document id: pmc-2010850, issue 1 upper right 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 nc sysclk nc vss nc vss nc vss reserved vss reserved vss nc vss vss vss vss a nc nc nc tck tms nc vddi reserved reserved reserved reserved reserved nc vddo vddo vddo vss b reserved nc vddi nc vddi tdi tdo nc reserved reserved reserved reserved vddi vddo vddo avdh vss c nc rc1fp vddi trstb vddi vddo vddi cmp reserved vddo reserved reserved nc vddo avdh avdh vss d avdh atb0[1] avdh avdh e atb1[1] tn[1] tp[1] vss f tn[3] tp[3] tn[2] tp[2] g avdh vddi nc vss h rp[1] rn[1] tn[4] tp[4] j vddi rp[2] rn[2] vss k vddi avdl14 rp[3] rn[3] l avdh rp[4] rn[4] vss m tn[6] tp[6] tn[5] tp[5] n vddi tn[7] tp[7] vss p rp[5] rn[5] tn[8] tp[8] r avdh vddi avdl13 vss t rp[7] rn[7] rp[6] rn[6] u
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 22 document id: pmc-2010850, issue 1 lower left vncncncnc w vss avdl6 vddi avdh yncncncnc aa vss nc nc vddi ab nc nc nc nc ac vss nc nc avdh ad nc nc avdl7 vddi ae vss nc nc vddi af nc nc nc nc ag vss nc vddi avdh ah nc nc nc nc aj vss nc nc atb1[2] ak avdh avdh atb0[2] avdh al vss avdh avdh vddo ale nc vddi vddo a[6] a[2] vddi vddo d[27] vddi nc nc vddi am vss avdh vddo vddo csb rdb vddi a[9] a[5] a[3] d[31] d[29] vddi d[25] vddi d[21] d[20] an vss vddo vddo vddo intb wrb nc a[10] a[7] a[4] a[0] d[30] d[28] d[26] nc d[22] d[19] ap vss vss vss vss nc vss a[11] vss a[8] vss a[1] vss nc vss d[24] d[23] d[18] 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 23 document id: pmc-2010850, issue 1 lower right csu_av dh avdl12 rp[8] rn[8] v avdl10 avdl11 tn[9] tp[9] w tn[10] tp[10] tn[11] tp[11] y vddi tn[12] tp[12] vss aa rp[9] rn[9] avdl9 vddi ab avdh rp[10] rn[10] vss ac rp[11] rn[11] rp[12] rn[12] ad vddi nc nc vss ae nc nc nc nc af avdh nc nc vss ag nc nc nc nc ah avdl8 nc nc vss aj nc nc res2 resk2 ak d[17] vddo d[13] d[11] d[8] vddo d[5] d[3] d[0] vddo nc nc vddo avdh avdh avdh vss al vddi d[15] vddi d[10] d[9] d[7] nc d[2] d[1] nc nc nc nc vddo avdh avdh vss am d[16] d[14] d[12] nc vddi d[6] d[4] vddi nc nc nc nc vddo vddo vddo avdh vss an nc vss vddi vss vddi vss nc vss nc vss nc vss vddo vss vss vss vss ap 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 24 document id: pmc-2010850, issue 1 8 pin description 8.1 pin description table pad name type pin no. function lvds ports (128 balls) rp[1] rn[1] rp[2] rn[2] rp[3] rn[3] rp[4] rn[4] rp[5] rn[5] rp[6] rn[6] rp[7] rn[7] rp[8] rn[8] rp[9] rn[9] rp[10] rn[10] rp[11] rn[11] rp[12] rn[12] analog lvds input j4 j3 k3 k2 l2 l1 m3 m2 r4 r3 u2 u1 u4 u3 v2 v1 ab4 ab3 ac3 ac2 ad4 ad3 ad2 ad1 receive serial data. the differential receive serial data links (rp[11:0]/rn[11:0]) carry the receive sbi336s or sonet/sdh sts-12 frame data from upstream sources in bit serial format. each differential pair rp[ x ]/rn[ x ] carries a constituent sbi336 or sts-12 stream. data on rp[ x ]/rn[ x ] is encoded in an 8b/10b format extended from ieee std. 802.3. the 8b/10b character bit ?a? is transmitted first and the bit ?j? is transmitted last. all rp[ x ]/rn[ x ] differential pairs must be frequency locked and phase aligned (within a certain tolerance) to each other. rp[11:0]/rn[11:0] are nominally 777.6 mbit/s data streams. any unused or n/c, but available inputs should be tied low using a 10 k resistor.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 25 document id: pmc-2010850, issue 1 pad name type pin no. function tp[1] tn[1] tp[2] tn[2] tp[3] tn[3] tp[4] tn[4] tp[5] tn[5] tp[6] tn[6] tp[7] tn[7] tp[8] tn[8] tp[9] tn[9] tp[10] tn[10] tp[11] tn[11] tp[12] tn[12] analog lvds output f2 f3 g1 g2 g3 g4 j1 j2 n1 n2 n3 n4 p2 p3 r1 r2 w1 w2 y3 y4 y1 y2 aa2 aa3 transmit serial data. the differential transmit working serial data links (tp[11:0]/tn[11:0]) carry the transmit sbi336s or sonet/sdh sts-12 frame data to a downstream sinks in bit serial format. each differential pair carries a constituent sts-12 stream. data on tp[ x ]/tn[ x ] is encoded in an 8b/10b format extended from ieee std. 802.3. the 8b/10b character bit ?a? is transmitted first and the bit ?j? is transmitted last. all tp[ x ]/tn[ x ] differential pairs are frequency locked and phase aligned (within a certain tolerance) to each other. tp[11:0]/tn[11:0] are nominally 777.6 mbit/s data streams. nse-8g control and clocking (5 balls) sysclk input a16 system clock. the system clock signal (sysclk) is the master clock for the nse-8g device. sysclk must be a 77.76 mhz clock, with a nominal 50% duty cycle. cmp and rc1fp are sampled on the rising edge of sysclk.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 26 document id: pmc-2010850, issue 1 pad name type pin no. function rc1fp input d16 receive serial interface frame pulse. the receive serial interface frame pulse signal (rc1fp) provides system timing for the receive serial interface. rc1fp is supplied in common to all devices in a system containing one or more nse-20g devices. in telecombus mode, rc1fp is set high once every four frames, in sbi mode without any ds0 switching, or when switching ds0s ( without cas) rc1fp is also set high once every four frames, or multiple thereof. when in sbi mode switching ds0s with cas rc1fp indicates signaling multiframe alignment by pulsing once every 48 frames or multiples thereof. a software configurable delay from rc1fp is used to indicate that the c1 multiframe boundary 8b/10b characters have been delivered on all the receive serial data links (rp[32:1]/rn[32:1]) and are ready for processing by the time-space-time switching elements. rc1fp is sampled on the rising edge of sysclk. reserved output c17 reserved pin, must be left floating cmp input d10 connection memory page . the connection memory page select signal (cmp) controls the selection of the connection memory page in the nse. when cmp is set high, connection memory page 1 is selected. when cmp is set low, connection memory page 0 is selected. changes to the connection memory page selection are synchronized to the boundary of the next c1fp frame or multiframe depending on the mode: 4-frame sbi/sbi336 mode: cmp is sampled at the c1 byte position of the incoming bus on the first frame of the four-frame multiframe. changes to the connection memory page selection are synchronized to the frame boundary (a1 byte position) of the next four-frame multiframe. 48-frame sbi/sbi336 mode: cmp is sampled at the c1 byte position of the incoming bus on the first frame of the 48-frame multiframe. changes to the connection memory page selection are synchronized to the frame boundary (a1 byte position) of the next 48-frame multiframe. telecombus mode: cmp is sampled at the c1 byte position of every frame on the incoming bus. changes to the connection memory pate selection are synchronized to the frame boundary (a1 byte position) of the next frame. cmp is sampled on the rising edge of sysclk at the rc1fp frame position. rstb input b18 reset enable bar. the active low reset signal (rstb) provides an asynchronous reset for the nse. rstb is a schmitt triggered input with an integral pull-up resistor
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 27 document id: pmc-2010850, issue 1 pad name type pin no. function microprocessor interface (49 balls) csb input am30 chip select bar. the active low chip select signal (csb) controls microprocessor access to registers in the nse- 8g device. csb is set low during nse-8g microprocessor interface port register accesses. csb is set high to disable microprocessor accesses. if csb is not required (i.e. register accesses controlled using rdb and wrb signals only), csb should be connected to an inverted version of the rstb input. rdb input am29 read enable bar. the active low read enable bar signal (rdb) controls microprocessor read accesses to registers in the nse-8g device. rdb is set low and csb is also set low during nse-8g microprocessor interface port register read accesses. the nse-8g drives the d[31:0] bus with the contents of the addressed register while rdb and csb are low. wrb input an29 write enable bar. the active low write enable bar signal (wrb) controls microprocessor write accesses to registers in the nse-8g device. wrb is set low and csb is also set low during nse-8g microprocessor interface port register write accesses. the contents of d[31:0] are clocked into the addressed register on the rising edge of wrb while csb is low.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 28 document id: pmc-2010850, issue 1 pad name type pin no. function d[31] d[30] d[29] d[28] d[27] d[26] d[25] d[24] d[23] d[22] d[21] d[20] d[19] d[18] d[17] d[16] d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] i/o am24 an23 am23 an22 al22 an21 am21 ap20 ap19 an19 am19 am18 an18 ap18 al17 an17 am16 an16 al15 an15 al14 am14 am13 al13 am12 an12 al11 an11 al10 am10 am9 al9 microprocessor data bus. the bi-directional data bus, d[31:0] is used during nse-8g microprocessor interface port register reads and write accesses. d[31] is the most significant bit of the data words and d[0] is the least significant bit. a[11 a[10] a[9] a[8] a[7] a[6] a[5] a[4] a[3] a[2] a[1] a{0] input ap28 an27 am27 ap26 an26 al26 am26 an25 am25 al25 ap24 an24 microprocessor address bus. the microprocessor address bus (a[11:0]) selects specific microprocessor interface port registers during nse-8g register accesses.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 29 document id: pmc-2010850, issue 1 pad name type pin no. function ale input al30 address latch enable. the address latch enable signal (ale) is active high and latches the address bus (a[11:0]) when it is set low. the internal address latches are transparent when ale is set high. ale allows the nse-8g to interface to a multiplexed address/data bus. ale has an integral pull up resistor. intb open drain output an30 interrupt request bar . the active low interrupt enable signal (intb) output goes low when an nse-8g interrupt source is active and that source is unmasked. intb returns high when the interrupt is acknowledged via an appropriate register access. intb is an open drain output. jtag port (5 balls) tck input b14 test clock. the jtag test clock signal (tck) provides timing for test operations that are carried out using the ieee p1149.1 test access port. tms input b13 test mode select. the jtag test mode select signal (tms) controls the test operations that are carried out using the ieee p1149.1 test access port. tms is sampled on the rising edge of tck. tms has an integral pull-up resistor. tdi input c12 test data input. the jtag test data input signal (tdi) carries test data into the nse-8g via the ieee p1149.1 test access port. tdi is sampled on the rising edge of tck. tdi has an integral pull-up resistor. tdo tri-state c11 test data output. thejtag test data output signal (tdo) carries test data out of the nse-8g via the ieee p1149.1 test access port. tdo is updated on the falling edge of tck. tdo is a tri-state output which is inactive except when scanning of data is in progress. trstb input d14 test reset bar. the active low jtag test reset signal (trstb) provides an asynchronous nse-8g test access port reset via the ieee p1149.1 test access port. trstb is a schmitt triggered input with an integral pull-up resistor. note that when trstb is not being used, it must be connected to the rstb input.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 30 document id: pmc-2010850, issue 1 pad name type pin no. function reserved reserved input c29 d29 b6 c6 d6 a7 b7 d7 c7 b8 c8 a9 b9 d9 c9 b10 c19 b19 c20 d20 b20 a20 d21 c21 b21 c22 d22 b22 a22 b23 c24 d24 b24 a24 reserved. must be left floating [internally pulled up]. external resistors (4 balls) res[2] res[1] analog input ak2 e33 reference resistor connection. an off-chip 3.16k ? 1% resistor is connected between these the positive resistor reference pin res and a kelvin ground contact resk. an on-chip negative feedback path will force the 1.20 v vref onto res, therefore forcing 252 a of current to flow through the resistor.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 31 document id: pmc-2010850, issue 1 pad name type pin no. function resk[2] resk[1] analog input ak1 e34 reference resistor connection. an off-chip 3.16 k ? 1% resistor is connected between these the positive resistor reference pin res and a kelvin ground contact resk. an on-chip negative feedback path will force the 1.20 v vref voltage onto res, therefore forcing 252 a of current to flow through the resistor. analog test bus (4 balls) atb0[2] atb0[1] analog ak32 e3 analog test bus for pmc validation and testing. this pin must be connected to gnd. atb1[2] atb1[1] analog aj31 f4 analog test bus for pmc validation and testing. this pin must be connected to gnd. digital core power (45 balls) vddi[44:0] power aa4 ab1 ae4 an10 an13 ap13 ap15 am15 am17 al18 am20 al21 am22 al24 am28 al28 ag32 ae31 ad31 aa31 w32 p31 n34 k31 t3 p4 the digital core power pins (vddi[44:0]) should be connected to a well-decoupled +1.8 v dc supply.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 32 document id: pmc-2010850, issue 1 pad name type pin no. function vddi[44:0] power l4k4 h3 c5 b11 d11 d13c13 c15 d15 c18 d18 a18 c23 b25 c26 d28 b29 c30 digital i/o power (34 balls) vddo[33:0] power al5 am4 an3 an4 an5 ap5 al8 al12 al16 al23 al27 al31 am31 am32 an31 an32 an33 a30 the digital i/o power pins (vddo[33:0]) should be connected to a well-decoupled +3.3 v dc supply.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 33 document id: pmc-2010850, issue 1 pad name type pin no. function vddo[33:0] power b30 b31 b32 c31 d30 d27 d23 d19 d12 d8 b2 b3 b4 c3 c4 d4 digital ground (72 balls) vss [71:0] ground a1 a2 a3 a4 a6 a8 a10 a12 a14 a19 a21 a23 a25 a27 a29 a31 a32 a33 a34 the digital ground pins (vss [71:0]) should be connected to gnd.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 34 document id: pmc-2010850, issue 1 pad name type pin no. function vss [71:0] ground ap1 ap2 ap3 ap4 ap6 ap8 ap10 ap12 ap14 ap16 ap21 ap23 ap25 ap27 ap29 ap31 ap32 ap33 ap34 b1 c1 d1 f1 h1 k1 m1 p1 t1 aa1 ac1 ae1 ag1 aj1 al1 am1 an1 b34 c34 d34 f34 h34
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 35 document id: pmc-2010850, issue 1 pad name type pin no. function vss [71:0] ground k34 m34 p34 w34 aa34 ac34 ae34 ag34 aj34 al34 am34 an34 analog power (8 balls) avdl[7:0] power f31 n33 w33 ad32 aj4 ab2 t2 l3 the analog power pins (avdl[7:0]) should be connected to a well-decoupled +1.8 v dc supply. these pins supply the rxlvs. clock synthesis 1.8 v power (6 balls) csu_avdl[5:0] power t31 t32 u32 w4 w3 v3 the clock synthesis pins (csu_avdl[5:0]) should be connected to a well-decoupled +1.8 v dc supply. these pins supply the csus. clock synthesis power (2 balls) csu_avdh[0:1] power u31 v4 these two pins should be connected to a well-decoupled +3.3 v dc supply.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 36 document id: pmc-2010850, issue 1 pad name type pin no. function analog i/o power (34 balls) avdh[33:0] power h4 m4 t4 ac4 ag4 al2 al3 al4 am2 am3 an2 c2 d2 d3 e1 e2 e4 b33 c32 c33 d31 d32 d33 ag31 ac31 w31 m31 h31 ak31 ak33 ak34 al32 al33 am33 the analog i/o power pins (avdh[33:0]) should be connected to a well-decoupled +3.3 v dc supply.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 37 document id: pmc-2010850, issue 1 pad name type pin no. function no connect (50 balls) nc[49:0] ag33 ap30 al29 an28 ap22 an20 al20 al19 ap17 an14 am11 ap11 an9 ap9 am8 an8 am7 al7 an7 ap7 al6 am6 an6 am5 h2 a5 b5 d5 c10 a11 b12 a13 c14 a15 b15 b16 c16 the no connect pins (nc[49:0]) should be left floating.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 38 document id: pmc-2010850, issue 1 pad name type pin no. function nc[49:0] d17 b17 a17 d25 c25 d26 b26 a26 c27 b27 c28 b28 a28 total 480 notes 1. all nse-8g inputs and bi-directional balls except the lvds links present minimum capacitive loading and operate at ttl logic levels. 2. inputs rstb, ale, tms, tdi and trstb have internal pull-up resistors. 3. all outputs have a minimum 8 ma drive capability ? this includes tdo, intb and d[31:0]). 4. the vddi and avdl power pins are not internally connected to each other. failure to connect these pins externally may cause malfunction or damage to the device. 5. the avdh, csu_avdh and vddo power pins are not internally connected to each other. failure to connect these pins externally may cause malfunction or damage to the device. 6. the vddi, vddo, avdh, csu_avdh and avdl power pins all share the common ground vss. 7. to prevent damage to the device and to ensure proper operation, power must be applied simultaneously to all 3.3 v power pins followed by power to all the 1.8 v power pins followed by input pins driven by signals. 8. to prevent damage to the device, power must first be removed from input pins followed by the removal of power from all the 1.8 v power supply pins followed by the simultaneous removal of power from all the 3.3 v power pins. 9. the 3.3 v supplies should never be less than the 1.8 v supplies at any time during power-up and power-down. 8.2 analog power filtering recommendations to achieve best performance of the lvds links, an analog filter network should be installed between the power balls and the supply.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 39 document id: pmc-2010850, issue 1 table 1 analog power filters rs cl ch notes csu avdh (2 balls) 3.3 ohm 100 nf 10 nf one filter network per vdd ball. csu avdl (6 balls) 0.47 ohm 4.7 f 10 nf one filter network per vdd ball. avdh (34 balls) 3.3 ohm 1.0 f 10 nf two vdd balls per filter network 1 . avdl (8 balls) 0 ohm 100 nf 10 nf one filter network per vdd ball. note 1. two power-gnd pairs can use the same filter. figure 7 analog power filter circuit r s c l c h supply vdd supply vss device vss device vdd
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 40 document id: pmc-2010850, issue 1 9 functional description 9.1 lvds overview the lvds family of cells allow the implementation of 777.6 mbit/s lvds links. a reference clock of 77.76 mhz is required. a generic lvds link according to ieee 1596.3-1996 is illustrated in figure 7 below. the transmitter drives a differential signal through a pair of 50 ? characteristic interconnects, such as board traces, backplane traces, or short lengths of cable. the receiver presents a 100 ? differential termination impedance to terminate the lines. included in the standard is sufficient common-mode range for the receiver to accommodate as much as 925 mv of common-mode ground difference. figure 8 generic lvds link block diagram ? zo=50 zo=50 ? 100? v op v on v ip v in transmitter interconnect receiver complete serdes transceiver functionality is provided. ten-bit parallel data is sampled by the line rate divided-by-10 clock (77.76 mhz sysclk) and then serialized at the line rate on the lvds output pins by a 777.6 mhz clock synthesized from sysclk. serial line rate lvds data is sampled and de-serialized to 10-bit parallel data. parallel output transfers are synchronized to a gated line rate divided-by-10 clock. the 10-bit data is passed to an 8b/10b decoding block. the gating duty cycle is adjusted such that the throughput of the parallel interface equals the receive input data rate (line rate +/- 100 ppm). it is expected that the clock source of the transmitter is the same as the clock source of the receiver to ensure the data throughput at both ends of the link are identical. data is guaranteed to contain sufficient transition density to allow reliable operation of the data recovery units by 8b/10b block coding and decoding provided by the t8te and r8td blocks.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 41 document id: pmc-2010850, issue 1 at the system level, reliable operation will be obtained if proper signal integrity is maintained through the signal path and the receiver requirements are respected. namely, a worst case eye opening of 0.7ui and 100 mv differential amplitude is needed. these conditions should be achievable with a system architecture consisting of board traces, two sets of backplane connectors, up to 1m of backplane interconnect. this assumes proper design of 100 ? differential lines and minimization of discontinuities in the signal path. due to power constraints, the output differential amplitude is approximately 350 mv the lvds system is comprised of the lvds receiver (rxlv), lvds transmitter (txlv), transmitter reference (txref), data recovery unit (dru), parallel to serial converter (piso and clock synthesis unit (csu). 9.1.1 lvds receiver (rxlv) the rxlv block is a 777.6 mbit/s low voltage differential signaling (lvds) receiver according to the ieee 1596.3-1996 lvds specification. the rxlv block is the receiver in figure 7, accepting 777.6 mbit/s lvds signals from the transmitter, over rp[x]/rn[x] pins, amplifying them and converting them to digital signals, then passing them to a data recovery unit (dru). holding to the ieee 1596.3-1996 specification, the rxlv has a differential input sensitivity better than 100 mv, and includes at least 25 mv of hysteresis. there are 12 rxlv blocks in the nse. 9.1.2 lvds transmitter (txlv) the txlv block is a 777.6 mbit/s low voltage differential signaling (lvds) transmitter according to the ieee 1596.3-1996 lvds specification. the txlv accepts 777.6 mbit/s differential data from a ?parallel-in, serial-out? (piso) circuit and then transmits the data off-chip as a lvds on tp[x]/tn[x] pins. the txlv uses a reference current and voltage from the txref block to control the output differential voltage amplitude and the output common-mode voltage. there are 12 instances of the txlv block in the nse-8g. 9.1.3 lvds transmit reference (txref) the txref provides an on-chip bandgap voltage reference (1.20 v 5%) and a precision current to the txlv (777.6 mbit/s lvds transmitter) block?s. the reference voltage is used to control the common-mode level of the txlv output, while the reference current is used to control the output amplitude. the precision currents are generated by forcing the reference voltage across an external, off-chip 3.16 k ? (1%) resistor. the resulting current is then mirrored through several individual reference current outputs, so each txlv receives its own reference current. there is one instance of the txref in the nse-8g.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 42 document id: pmc-2010850, issue 1 9.1.4 data recovery unit (dru) the dru is a fully integrated data recovery and serial to parallel converter that can be used for 777.6 mbit/s nrz data. 8b/10b block code is used to guarantee transition density for optimal performance. the dru recovers data and outputs a ten-bit word synchronized with a line rate divided by ten, gated clock to allow frequency deviations between the data source and the local oscillator. the output clock is not a recovered clock. the dru accumulates 10 data bits and outputs them on the next clock edge. if 10-bits are not available for transfer at a given clock cycle, the output clock is gated. the dru provides moderate high frequency jitter tolerance suitable for inter-chip serial link applications. it can support frequency deviations up to 100 ppm. there are 12 instances of the dru on the nse-8g. 9.1.5 parallel to serial converter (piso) the piso is a parallel-to-serial converter designed for high-speed transmit operation, supporting up to 777.6 mbit/s. there are 12 instances of the piso on the nse-8g. 9.1.6 clock synthesis unit (csu) the csu is a fully integrated clock synthesis unit. it generates low jitter multi-phase differential clocks at 777.6 mhz for the use by the transmitter. there is one instance of the csu on the nse-8g. 9.2 receive 8b/10b frame aligner (r8td) the receive 8b/10b serial sbi336s bus frame aligner, r8td, frames to the receive stream to find 8b/10b character boundaries. it also contains a fifo to bridge between the timing domain of the receive lvds links and the system clock timing domain. the r8td blocks perform framing and elastic store functions on data retrieved from the receive lvds links, rp[x]/rn[x]. 9.2.1 fifo buffer the fifo buffer sub-block provides isolation between the timing domains of the associated receive lvds link and that of the system clock, sysclk. data with arbitrary alignment to the 8b/10b characters, are written into a 10-bit by 24-word deep fifo at the link clock rate. data is read from the fifo at every sysclk cycle.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 43 document id: pmc-2010850, issue 1 9.3 transmit 8b/10b encoder (t8te) the transmit 8b/10b encoder blocks, t8te, construct an 8b/10b character stream from an incoming translated sbi336 or telecombus carrying an sts-12/stm-4 equivalent channelized stream. the t8te block corrects the running disparity of an 8b/10b character stream and buffers data in a fifo before transmission to the transmit serializer block. a total of 32 t8te blocks are instantiated in the nse-20g device. in sbi mode, these blocks encode the sbi336s stream as shown in table 2. when configured for synchronous mode for ds0 switching, the 8b/10b encoder transmits cas signaling multiframe alignment across the sbi336s interface by generating a c1fp character every 48 frame times. when not configured for ds0 switching, the c1fp character is sent every four frames. 9.3.1 sbi336s 8b/10b character encoding table 2 shows the mapping of sbi336s bus control bytes and signals into 8b/10b control characters. the linkrate octet in location v4, v1 and v2, the in-band programming channel, the v3 octet when it contains data are all carried as data. justification requests for master timing are carried in the v5 character so there are three v5 characters used, nominal, negative timing adjustment request, positive timing adjustment request. table 2 sbi336s character encoding code group name curr. rd- abcdei fghj curr. rd+ abcdei fghj encoded signals description common to all link types k28.5 001111 1010 110000 0101 ic1fp=?b1 c1fp frame and multiframe alignment k23.7- 111010 1000 - overhead bytes (columns 1-60 or 1-72 except for c1 and in-band programming channel), v3 or h3 byte except during negative justification, byte after v3 or h3 byte during positive justification, unused bytes in fraction rate links asynchronous t1/e1 links k27.7- 110110 1000 - v5 byte, no justification request k28.7- 001111 1000 - v5 byte, negative justification request k29.7- 101110 1000 - v5 byte, positive justification request synchronous t1/e1 links k27.7- 110110 1000 - v5 byte asynchronous ds3/e3 links k27.7- 110110 1000 - v5 byte, no justification request k28.7- 001111 1000 - v5 byte, negative justification request* k29.7- 101110 1000 - v5 byte, positive justification request* fractional rate links k28.7- 001111 1000 - v5 byte, send one extra byte request**
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 44 document id: pmc-2010850, issue 1 code group name curr. rd- abcdei fghj curr. rd+ abcdei fghj encoded signals description k29.7- 101110 1000 - v5 byte, send one less byte request** floating transparent virtual tributaries k27.7- 110110 1000 - v5 byte iv5=1, idata[0,4] = erdi[1:0] = ?b00, idata[5] = rei = ?b0 k27.7+ - 001001 0111 v5 byte iv5=1, idata[0,4] = erdi[1:0] = ?b00, idata[5] = rei = ?b1 k28.7- 001111 1000 - v5 byte iv5=1, idata[0,4] = erdi[1:0] = ?b01, idata[5] = rei = ?b0 k28.7+ - 110000 0111 v5 byte iv5=1, idata[0,4] = erdi[1:0] = ?b01, idata[5] = rei = ?b1 k29.7- 101110 1000 - v5 byte iv5=1, idata[0,4] = erdi[1:0] = ?b10, idata[5] = rei = ?b0 k29.7+ - 010001 0111 v5 byte iv5=1, idata[0,4] = erdi[1:0] = ?b10, idata[5] = rei = ?b1 k30.7- 011110 1000 - v5 byte iv5=1, idata[0,4] = erdi[1:0] = ?b11, idata[5] = rei = ?b0 k30.7+ - 100001 0111 v5 byte iv5=1, idata[0,4] = erdi[1:0] = ?b11, idata[5] = rei = ?b1 * note there can be multiple v5s per sbi frame when in ds3 or e3 mode but only one justification can occur per sbi frame. positive and negative justification request through v5 required by the sbi336s interface should be limited to one per frame. ** note fractional rate links are symmetric in the transmit and receive direction over sbi336s. when using clock slave mode with a fractional rate link the clock master makes single byte adjustments to the slaves rate once per frame. 9.3.2 serial telecombus 8b/10b character encoding table 3 shows the mapping of telecombus control bytes and signals into 8b/10b control characters. when the telecombus control signals conflict each other, the 8b/10b control characters are generated according to the sequence of the table, with the characters at the top of the table taking precedence over those lower in the table.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 45 document id: pmc-2010850, issue 1 table 3 serial telecombus character encoding code group name curr. rd- abcdei fghj curr. rd+ abcdei fghj encoded signals description high order path termination (hpt) mode k28.5 001111 1010 110000 0101 ic1fp=?b1 ipl=?b0 c1fp frame and multiframe alignment k28.0- 001111 0100 - ipl=?b0 high-order path h3 byte position, no negative justification event. k28.0+ - 110000 1011 ipl=?b0 high-order path pso byte position, positive justification event. k28.6 001111 0110 110000 1001 ic1fp=?b1, ipl=?b1 high-order path frame alignment (j1). low order path termination (lpt) mode k28.4+ - 110000 1101 itais=?b1 low-order path ais. k27.7- 110110 1000 - iv5=?b1, idata[0,4] = erdi[1:0] = ?b00, idata[5] = rei = ?b0 low order path frame alignment. erdi and rei are encoded in the v5 byte. k27.7+ - 001001 0111 iv5=?b1, idata[0,4] = erdi[1:0] = ?b00, idata[5] = rei = ?b1 low order path frame alignment. erdi and rei are encoded in the v5 byte. k28.7- 001111 1000 - iv5=?b1, idata[0,4] = erdi[1:0] = ?b01, idata[5] = rei = ?b0 low order path frame alignment. erdi and rei are encoded in the v5 byte. k28.7+ - 110000 0111 iv5=?b1, idata[0,4] = erdi[1:0] = ?b01, idata[5] = rei = ?b1 low order path frame alignment. erdi and rei are encoded in the v5 byte. k29.7- 101110 1000 - iv5=?b1, idata[0,4] = erdi[1:0] = ?b10, idata[5] = rei = ?b0 low order path frame alignment. erdi and rei are encoded in the v5 byte. k29.7+ - 010001 0111 iv5=?b1, idata[0,4] = erdi[1:0] = ?b10, idata[5] = rei = ?b1 low order path frame alignment. erdi and
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 46 document id: pmc-2010850, issue 1 rei are encoded in the v5 byte. k30.7- 011110 1000 - iv5=?b1, idata[0,4] = erdi[1:0] = ?b11, idata[5] = rei = ?b0 low order path frame alignment. erdi and rei are encoded in the v5 byte. k30.7+ - 100001 0111 iv5=?b1, idata[0,4] = erdi[1:0] = ?b11, idata[5] = rei = ?b1 low order path frame alignment. erdi and rei are encoded in the v5 byte. k23.7- 111010 1000 000101 0111 itpl=?b0 non low-order path payload bytes. 9.3.3 serial sbi336s and telecombus alignment the alignment functionality preformed by each receiver can be broken down into two parts, character alignment and frame alignment. character alignment finds the 8b/10b character boundary in the arbitrarily aligned incoming data. frame alignment finds sbi336s or telecombus frame and multiframe boundaries within the serial link. the character and frame alignment are expected to be robust enough for operation over a cabled interconnect. 9.3.4 character alignment block character alignment locates character boundaries in the incoming 8b/10b data stream. the character alignment algorithm may be in one of two states, in-character-alignment state and out- of-character-alignment state. the two states of the character alignment algorithm is shown in figure 8. when the character alignment state machine is in the out-of-character-alignment state, it maintains the current alignment, while searching for a c1fp character. if it finds the c1fp character, it will re-align to the c1fp character and move to the in-character-alignment state. the c1fp character is found by searching for the 8b/10b c1fp character, k28.5+ or k28.5-, simultaneously in ten possible bit locations. while in the in-character-alignment state, the state machine monitors lcvs. if 5 or more lcvs are detected within a 15 character window the character alignment state machine transitions to out-of-character-alignment state. the special characters listed in table 2 and table 3 are ignored for lcv purposes. upon return to in- character-alignment state the lcv count is cleared.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 47 document id: pmc-2010850, issue 1 figure 9 character alignment state machine out-of- character- alignment in- character- alignment 5-in-15 lcvs found c1fp character 9.3.5 frame alignment frame alignment locates sbi or telecombus frame and multiframe boundaries in the incoming 8b/10b data stream. the frame alignment state machine may be in one of two states, in-frame- alignment state and out-of-frame-alignment state. each sbi336s frame is 125 s in duration. in sbi mode: encoded over the sbi336s frame alignment is sbi336s multiframe alignment which is every four sbi336s frames or 500 s. when carrying ds0 traffic in synchronous mode, signaling multiframe alignment is also necessary and is also encoded over sbi336s alignment. signaling multiframe alignment is every 24 frames for t1 links and every 16 frames for e1 links, therefore signaling multiframe alignment covering both t1 and e1 multiframe alignment is every 48 sbi336s frames or 6ms. therefore c1fp characters are sent every four or every 48 frames. in telecombus mode: encoded over the serial link is the tributary multiframe alignment which is every 4 frames or 500 s. multiframe alignment is required so that a downstream device can extract the t1 or e1 data from the tributary. the multiframe information is preserved by only sending out c1fp characters every four frames.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 48 document id: pmc-2010850, issue 1 the frame alignment state machine establishes frame alignment over the link and is based on the frame and not the multiframe alignments. when the frame alignment state machine is in the out- of-frame-alignment state, it maintains the current alignment, while searching for a c1fp character. when it finds the c1fp character the state machine transitions to the in-frame- alignment state. while in the in-frame-alignment state, the state machine monitors out-of-place c1fp characters. out-of-place c1fp characters are identified by maintaining a frame counter based on the c1fp character. the counter is initialized by the c1fp character when in the out-of- character-alignment state, and is unaffected in the in-character-alignment state. if three consecutive c1fps have been found that do not agree with the expected location as defined by the frame counter, the state will change to out-of-frame-alignment state. the frame alignment state machine is also sensitive to character alignment. when the character alignment state machine is in the out-of-character-alignment state, the frame alignment state machine is forced out-of-alignment, and is held in that state until the character alignment state machine transitions to the in-character alignment state. figure 10 frame alignment state machine out-of- frame- alignment in-frame- alignment 3 consecutive out-of-place c1fps or out-of-character alignment found c1fp and not (out-of-character alignment)
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 49 document id: pmc-2010850, issue 1 9.3.6 sbi336s multiframe alignment sbi336s multiframe alignment is communicated across the link by controlling the frequency of the c1fp character. the most frequent transmission of the c1fp character is every four sbi336s frame times. this is the sbi336s multiframe and is used when there are no synchronous tributaries requiring signalling multiframe alignment on the sbi336s bus. when there are synchronous tributaries on the sbi336s bus the c1fp character is transmitted every 48 frame times. this is the cas signaling multiframe and is the lowest common multiple of the 24 frame t1 multiframe and the 16 frame e1 multiframe. the sbi336s multiframe and signaling multiframe alignment is based a free running multiframe counter that is reset with each c1fp character received. under normal operating conditions each received c1fp character will coincide with the free running multiframe counter. sbi336s multiframe alignment is always required, sbi336s signaling multiframe alignment is optional and only required when synchronous tributaries are supported with ds0 level switching. 9.4 ds0 cross bar switch (dcb) each of 12 r8td blocks provides an eight-bit data signal on each 77.76 mhz clock edge. these signals are the sts-12 frame aligned ingress octets. likewise, each of 12 egress t8te blocks expects to receive a sts-12 frame aligned signal on each clock edge. the ds0 cross bar switch (dcb) connects these inputs to these outputs. the dcb constitutes a space switch that connects each output to some input during each clock period in the sts-12 frame structure. the sts-12 frame structure consists of 12*9*90 = 9720 octets (of overheads and payload). being a ds0 granularity space switch, the dcb must provide separate switch settings for each of these 9720 octet times. these 9720 switch settings are stored in an on-chip sram. each of twelve egress ports must be told which of each of twelve ingress ports it should read during each of the 9720 clock periods. five bits are required to specify which ingress port should be read by each output. thus, we require 9720 words of five bits each for twelve egress ports. thus each clock period requires 12 *5 = 60 bits. to support controlled switchover from one set of switch settings to another, we require two banks of 9720 words each. the aggregate memory requirement is 2 x 9720 x 60b = 1,166,400b of sram. table 4 illustrates the mapping of this memory. each control page in the table is a vector of 60 bits containing five bits (specifying the source port) for each of 12 egress ports. one page will be on-line translating ports in the core switch while the other is offline for cpu update. when the new configuration is ready, and the appropriate system synchronized frame boundary arrives, the pages will be swapped.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 50 document id: pmc-2010850, issue 1 table 4 switching control ram layout control page 0 control page 1 ram address sts row col sts row col 0111111 1211211 ?? 9719 12 9 90 12 9 90 the multiplexers that select the inputs for each egress port are straight forward 12 to-1 multiplexers. they require five bits of control during each 77.76 mhz clock cycle. their outputs go to the t8tes. this design permits unicast, multicast, and broadcast. 9.5 clock synthesis and transmit reference digital wrapper (cstr) the cstr contains the configuration registers for the csu and txref lvds analog locks. 9.6 fabric latency the flow of octets from ingress lvds to egress lvds has variable latency, depending on the timing of the arriving lvds stream, and the clock variation on the egress lvds drivers. a reasonable estimate of the nse?s latency can be arrived at by making assumptions about the depths of the receive and transmit fifos: we assume the ?c1? timing is set to maintain about four samples in the ingress fifo; the egress fifo is designed to be centered at four samples ? so typically delay due to fifos will be 8 clock cycles. the latency through the space switch stage is three clock cycles. data latency through the analog blocks is around 90 ns. the typical latency of the nse-8 g is 24 clock cycles or 308 ns. with worst case conditions in both fifos, latency rises to 36 clock cycles or 463 ns. 9.7 jtag support the nse-8g provides jtag support for testing device interconnection on a pc board. 9.8 microprocessor interface the microprocessor interface block provides the logic required to interface the normal mode and test mode registers within the nse-8g to a generic microprocessor bus. the normal mode registers are used during normal operation to configure and monitor the nse. the register set is accessed as shown in the register memory map table below. addresses that are not shown are not used and must be treated as reserved.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 51 document id: pmc-2010850, issue 1 9.9 in-band link controller (ilc) in order to permit centralized control of distributed nse/sbs fabrics from the nse-8g microprocessor interface (for applications in which nses are located on fabric cards, and sbss are located on multiple line cards), an in-band signaling channel is provided between the nse-8g and the sbs over the serial sbi336s interface. each nse-8g can control up to 12 sbss that are attached by the lvds links. the nse-sbs in-band channel is full duplex, but the nse-8g has active control of the link. the in-band channel is carried in the first 36 columns of four rows of the sbi structure, rows 3, 6, 7 and 8. the overall in-band channel capacity is thus 36*4*64 kb/s = 9.216 mbit/s. each 36 bytes per row allocated to the in-band signaling channel is its own in-band message between the end points. four bytes of each 36 byte inband message are reserved for end-to-end control information and error protection, leaving 8.192 mbit/s available for data transfer between the end points. the data transferred between the end points has no fixed format, effectively providing a clear channel for packet transfer between the attached microprocessors at each of the lvds link terminating devices. the user is able to send and receive any packet up to 32 bytes in length. the last two reserved bytes of the 36 byte in-band message is a crc-16 which detects errors in the message. this block provides a microprocessor interface to the in-band signaling channel. this in-band channel is expected to be used almost entirely to carry out switching control changes in the sbss. to configure a ds0 in an sbs device most often requires a local microprocessor to write to one memory location consisting of a 16-bit address and a 16-bit data. using this as a baseline and assuming an efficient use of the in-band channel bandwidth, we can set a maximum of (32bytes/row * 4 rows/frame * 8000 frames/sec / 4 bytes/write) 256,000 ds0 configurations per second. considering that configuring a t1 when switching ds0s requires 27 ds0 writes, indicates that the in-band signaling channel bandwidth sets maximum limit of over 9000 t1 configurations per second. in real life these limits will not be achieved but this shows that the in-band link should not be the bottleneck. in telecombus mode, this same configuration will require only three writes per t1 link. another more efficient communication scheme could be used to increase this performance. in n+1 protected architectures, it is likely that full configuration of a port card will be necessary during the switchover. this would require the entire connection memory be reconfigured. assuming connections for overhead bytes are also reconfigured, the fastest that a complete reconfiguration can take place is 9720 register writes for each of the two configuration pages in the sbs. this equates to (2 * 9720 writes * 4 bytes/write / (32 bytes/row * 4 rows/frame * 8000 frames/second)) 76 milliseconds. it is also possible that the spare card could hold all the connection configurations for all the port cards it is protecting locally, for even faster switch over.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 52 document id: pmc-2010850, issue 1 9.9.1 in-band signaling channel fixed overhead the in-band link controller block generates and terminates two bytes of fixed header and a crc-16 per every 32 byte in-band message (total 36 bytes). the two byte header provides control and status between devices at the ends of the lvds link. the crc-16 is calculated over the 32 byte (and header - 34 bytes) in-band message and provides the terminating end the ability to detect errors in the in-band message. the format of the in-band message and header bytes is shown in figure 11 and figure 12. figure 11 in-band signaling channel message format 1 byte 1 byte 32 bytes 2 bytes header1 header2 free format information crc-16 figure 12 in-band signaling channel header format header1 bit 7 bit 6 bit 5 bit4 bit3 bit2 bit1 bit 0 valid link[1:0] page[1:0] user[2:0] header2 bit 7 bit 6 bit 5 bit4 bit3 bit2 bit1 bit 0 aux[7:0] table 5 in-band message header fields field name nse-8g to sbs sbs to nse valid message slot contains a message(1) or is empty(0). if empty this message will not be put into rx message fifo (other header information processed as usual) message slot contains a message(1) or is empty(0). if empty this message will not be put into rx message fifo (other header information processed as usual) link[1:0]# these bits are optional for sbi336s devices, intended for devices which have multiple redundant links. each bit either indicates which link to use, working(0) or protect(1) when sourced from the master device, or which link is being used, when sourced from the slave device. other algorithms are possible to indicate working or protect over these 2 bits but all sbi336s devices must be able to revert back to this meaning. transmitted immediately. these bits are optional for sbi336s devices, intended for devices which have multiple redundant links. each bit either indicates which link to use, working(0) or protect(1) when sourced from the master device, or which link is being used, when sourced from the slave device. other algorithms are possible to indicate working or protect over these 2 bits but all sbi336s devices must be able to revert back to this meaning.transmitted immediately.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 53 document id: pmc-2010850, issue 1 field name nse-8g to sbs sbs to nse page[1:0]# each bit indicates which control page to use, page 1 or 0, two bits, bit 1 for the ingress msu and bit 0 for the egress msu. only transmitted from the beginning of the first message of the frame each bit shows current control page in use, page 1 or 0, two bits, bit 1 for the ingress msu and bit 0 for the egress msu. only transmitted from the beginning of the first message of the frame. user[2:0]# user defined register indication to sbs reflected in the sbs as external hardware signal outputs. transmitted immediately. user defined register indication to nse-8g from external hardware inputs to the sbs. transmitted immediately. aux[7:0]# user defined auxiliary register indication to sbs. transmitted immediately. user defined auxiliary register indication to nse. transmitted immediately. # change in these bits(received side) will not be processed if the received message crc-16 indicates an error. interrupts can be generated when crc errors are detected or the user or link bits change state. there is no inherent flow control provided by the in-band link controller. the attached microprocessor is able to provide flow control via interrupts when the in-band message fifo overflows and via the user and auxiliary bits in the header. as each message arrives, the crc-16 and valid bit is checked; if the valid bit is not set the message is discarded, if it fails the crc check it is flagged as being in error and an interrupt is generated if enabled. if the crc-16 is ok, regardless of the valid bit, the page link, user and aux bits are passed on immediately. if the fifo erroneously overflows, an interrupt is generated. 9.10 microprocessor interface the following register map, table 6, shows the registers used to provide control of the nse. the first 100h addresses provide access to the top level nse-8g configuration and control registers, the clock synthesis units through the cstr blocks and the dso crossbar (dcb) the dcb is the space switch at the core of the nse. from 100h are 12 identical, 20h spaces used to control the ports of the nse-8g on an individual basis. each port has an in-band link controller (ilc), an 8b/10b encoder (t8te) and an 8b/10b decoder (r8td). these blocks provide functions specific to the ports such as line code violation counts (for data integrity monitoring) and receive and transmit in-band link message buffers. only port 0 is fully described as the other ports are identical, being incrementally distributed from address 100h in 20h steps.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 54 document id: pmc-2010850, issue 1 table 6 nse-8g register map address register 000 nse-8g master reset 001 nse-8g individual channel reset 002 nse-8g master jtag id 003 sbs page select ? page 0 004 sbs page select ? page 1 005 nse-8g master interrupt source 006 nse-8g master ilc interrupt source 007 nse-8g master r8td interrupt source 008 nse-8g master t8te interrupt source 009 nse-8g master clock monitor 00a nse-8g dcb cmp select 00b nse-8g master interrupt enable 00c nse-8g subsystem interrupt enable 00d nse-8g r8td tip 00e sbs user bits 0 00f sbs user bits 1 010 sbs user bits 2 011 nse-8g free user register 012 r8td_rx_c1 pulse monitor register 013 unexpected r8td_rx_ c1 interrupt register 014 missing r8td_rx_ c1 interrupt register 015 unexpected r8td_rx_ c1 interrupt enable register 016 missing r8td_rx_ c1 interrupt enable register 017 r8td c1 disable 01c-01f reserved 020 cstr #1 control 021 cstr #1 interrupt enable and csu lock status 022 cstr #1 interrupt indication 023 reserved 024 reserved 025 reserved 026 reserved 027-03f reserved 040 reserved 041 reserved 042 reserved 043 reserved 044 dcb configuration port 11-6 register 045 dcb configuration port 5-0 register
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 55 document id: pmc-2010850, issue 1 address register 046 dcb configuration output register 047 dcb access mode register 048 dcb c1 delay (rc1fp) register 04a dcb frame size register 04c dcb configuration register 04d dcb interrupt register 04e ? 0ff reserved 100-1ff port register set 0 ? port 0 (channel 0) 100 port register set 0: r8td control and status 101 port register set 0: r8td interrupt status 102 port register set 0: r8td lcv count 103 port register set 0: rxlv and dru control 0106 ? 107 port register set 0: reserved 108 port register set 0: t8te control and status 109 port register set 0: t8te interrupt status 10a port register set 0: t8te time-slot configuration #1 10b port register set 0: t8te time-slot configuration #2 10c port register set 0: t8te test pattern 10d port register set 0: txlv and piso control 10f port register set 0: reserved 110 port register set 0: ilc transmit message fifo data 111 port register set 0: ilc transmit control 112 port register set 0: ilc transmit status and fifo synch 113 port register set 0: ilc receive message fifo data 114 port register set 0: ilc receive control 115 port register set 0: ilc receive status and fifo synch 116 port register set 0: ilc interrupt enable and control 117 port register set 0: ilc interrupt reason register 118-11f reserved 120-13f port register set 1 ? port 1 (channel 1) 140-15f port register set 2 ? port 2 (channel 2) 160-17f port register set 3 ? port 3 (channel 3) 180-19f port register set 4 ? port 4 (channel 4) 1a0-1bf port register set 5 ? port 5 (channel 5) 1c0-1df port register set 6 ? port 6 (channel 6) 1e0-1ff port register set 7 ? port 7 (channel 7) 200-21f port register set 8 ? port 8 (channel 8) 220-23f port register set 9 ? port 9 (channel 9) 240-25f port register set 10 ? port 10 (channel 10) 260-27f port register set 11 ? port 11 (channel 11)
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 56 document id: pmc-2010850, issue 1 address register 280-29f port register set 12 ? port 12 (channel 12 2a0-7ff reserved 800 ? fff reserved for test notes on register memory map: 1. for all register accesses, csb must be low. 2. addresses that are not shown must be treated as reserved.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 57 document id: pmc-2010850, issue 1 10 normal mode register description normal mode registers are used to configure and monitor the operation of the nse. normal mode registers (as opposed to test mode registers) are selected when a[11] is set low. notes on normal mode register bits: 1. writing values into unused register bits has no effect. however, to ensure software compatibility with future, feature-enhanced versions of this product, unused register bits must be written with logic 0. reading back unused bits can produce either a logic one or a logic 0; hence, unused register bits should be masked off by software when read. 2. all configuration bits that can be written into can also be read back. this allows the processor controlling the tsb to determine the programming state of the block. 3. writeable normal mode register bits are cleared to logic 0 upon reset unless otherwise noted. 4. writing into read-only normal mode register bit locations does not affect nse-8g operation unless otherwise noted. 5. for registers above 100h, only a one port set of the 12 ports are shown. the register addresses are shown for example as: 0100h + n*20h, n here is the port number between 0 and 11. this is done to prevent unnecessary duplication of otherwise identical register sets.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 58 document id: pmc-2010850, issue 1 register 000h: nse-8g master reset bit type function default bit 31 r/w dreset 0 bit 30 r/w areset 0 bit 29:0 r unused x this register allows separate software reset of digital and analog circuitry on the nse. areset the areset bit allows the analog circuitry in the nse-8g to be reset under software control. if the areset bit is a logic one, all the nse-8g analog circuitry is held in reset. areset must be held at logic one for at least 100us to ensure correct reset of the csu. this bit is not self-clearing. therefore, a logic zero must be written to bring the nse-8g out of reset. holding the nse-8g in a reset state places it into a low power, analog stand-by mode. a hardware reset clears the areset bit, thus negating the analog software reset. dreset the dreset bit allows the digital circuitry in the nse-8g to be reset under software control. if the dreset bit is a logic one, all the nse-8g digital circuitry is held in reset. this bit is not self-clearing. therefore, a logic zero must be written to bring the nse-8g out of reset. holding the nse-8g in a reset state places it into a low power, digital stand-by mode. a hardware reset clears the dreset bit, thus negating the digital software reset.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 59 document id: pmc-2010850, issue 1 register 001h: nse-8g individual channel reset bit type function default bit 11:0 r/w reset[11:0]* 1 this register allows power saving by holding individual channels in reset. reset[n] the reset[n] bit allows the channel circuitry in the nse-8g to be reset under software control. if the reset[n] bit is a logic one, the nse-8g channel circuitry for a particular channel is held in reset. reset[n] does not affect the reset of the csu. this bit is not self- clearing. therefore, a logic zero must be written to bring the channel out of reset. holding the channel in a reset state places it into a low power, analog stand-by mode. a hardware reset or software dreset bit 000h sets the reset[n] bit.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 60 document id: pmc-2010850, issue 1 register 002h: nse-8g master jtag id bit type function default hex bit 31:28 r id[3:0] 0h bit 27:12 r devid[15:0] 8621h bit 11:0 r jtag identification code [mid[10:0] & jid] 0cdh the nse-8g master jtag id registers hold the jtag identification code for the device. the device revision number and device id are available through these registers. id[3:0] the id bits can be read to provide a binary nse-8g revision number. devid[15:0] the devid bits can be read to distinguish the nse-8g from other members of the nse-8g family of devices. mid[10:0] the mid bits provide the manufacturer identity field in the jtag identification code. jid the jid bit is bit 0 in the jtag identification code.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 61 document id: pmc-2010850, issue 1 register 003h: sbs page select ? page 0 bit type function default bit 11:0 r/w page0_sbs[11:0]* 0 page0_sbs[n] this bit will be the page 0 bit sent to sbsn over the in-band channel ? where n is any sbs connected to lvds links numbered from 0 to 11*.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 62 document id: pmc-2010850, issue 1 register 004h: sbs page select ? page 1 bit type function default bit 11:0 r/w page1_sbs[11:0]* 0 page1_sbs[n] this bit will be the page 1 bit sent to sbsn over the in-band channel ? where n is any sbs connected to lvds links numbered from 0 to 11*.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 63 document id: pmc-2010850, issue 1 register 005h: nse-8g master interrupt source bit type function default bit 31:8 r unused x bit 7 r r8c1extraint 0 bit 6 r r8c1missint 0 bit 5 r reserved 0 bit 4 r csu1int 0 bit 3 r r8tdint 0 bit 2 r t8teint 0 bit 1 r ilcint 0 bit 0 r dcbint 0 r8c1extraint if the r8c1extraint bit is a logic one, an interrupt of unexpected c1 character in one of the r8td_c1_int blocks has occurred. the source of the r8c1extraint bit comes from the register 013h. r8c1missint if the r8c1missint bit is a logic one, an interrupt of missing c1 characters in one of the r8td_c1_int blocks has occurred. the source of the r8c1missint bit comes from the register 014h. csu1int if the csu1int bit is a logic one, an interrupt has been generated by csu #1. the cstr interrupt register must be read to clear this interrupt. r8tdint if the r8tdint bit is a logic one, an interrupt has been generated by one of the r8td blocks. the internal r8td interrupt register must be read to clear this interrupt. which r8td caused the interrupt can be ascertained by reading the nse-8g r8td interrupt source register. t8teint if the t8teint bit is a logic one, an interrupt has been generated by one of the t8te blocks. the internal t8te interrupt register must be read to clear this interrupt. which t8te caused the interrupt can be ascertained by reading the nse-8g t8te interrupt source register.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 64 document id: pmc-2010850, issue 1 ilcint if the ilcint bit is a logic one, an interrupt has been generated by one of the ilc blocks. the relevant ilc interrupt register must be read to clear this interrupt. which ilc caused the interrupt can be ascertained by reading the nse-8g ilc interrupt source register. dcbint if the dcbint bit is a logic one, an interrupt has been generated by the dcb block. the dcb interrupt register must be read to clear this interrupt.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 65 document id: pmc-2010850, issue 1 register 006h: nse-8g master ilc interrupt source bit type function default bit 11:0 r ilcint[11:0]* 0 ilcint[n] if the ilcint[n] bit is a logic one, an interrupt has been generated by that ilc block. the relevant ilc interrupt register must be read to clear this interrupt.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 66 document id: pmc-2010850, issue 1 register 007h: nse-8g master r8td interrupt source bit type function default bit 11:0 r r8tdint[11:0]* 0 r8tdint[n] if the r8tdint[n] bit is a logic one, an interrupt has been generated by that r8td block. the relevant r8td interrupt register must be read to clear this interrupt.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 67 document id: pmc-2010850, issue 1 register 008h: nse-8g master t8te interrupt source bit type function default bit 11:0 r t8teint[11:0]* 0 t8teint[n] if the t8teint[n] bit is a logic one, an interrupt has been generated by that t8te block. the relevant t8te interrupt register must be read to clear this interrupt
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 68 document id: pmc-2010850, issue 1 register 009h: nse-8g master clock monitor bit type function default bit 31:2 r unused x bit 1 r rc1fpa x bit 0 r sysclka x when a monitored clock signal makes a low to high transition, the corresponding register bit is set high. the bit will remain high until this register is read, at which point all the bits in this register are cleared. a lack of transitions is indicated by the corresponding register bit reading low. this register should be read at periodic intervals to detect clock failures. sysclka the sysclk active bit (sysclka) detects low to high transitions on the sysclk input. sysclka is set high on a rising edge of sysclk, and is set low when this register is read. rc1fpa the rc1fp active bit (rc1fpa) detects low to high transitions on the rc1fp input. rc1fpa is set high on a rising edge of rc1fp, and is set low when this register is read.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 69 document id: pmc-2010850, issue 1 register 00ah: nse-8g dcb cmp select bit type function default bit 31:2 r unused x bit 1 r/w cmp_src 0 bit 0 r/w cmp_val 0 the connection memory page select signal (cmp) controls the selection of the connection memory page in the nse. when cmp is set high, connection memory page 1 is selected. when cmp is set low, connection memory page 0 is selected. changes to the connection memory page selection are synchronized to the boundary of the next c1fp multiframe. this register controls a software override to the cmp pin. cmp_src this bit dictates whether cmp is to be sourced from software when set to ?1? or from the external cmp pin when set to 0. cmp_val cmp_val is used to provide the cmp signal when cmp_src is set to ?1? other wise this bit is ignored.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 70 document id: pmc-2010850, issue 1 register 00bh: nse-8g interrupt enable register bit type function default bit 31:1 r unused x bit 0 r/w inte 0 this register allows the cpu to disable or enable nse-8g interrupts with a single write. inte this bit, when ?1?, enables the intb pin on the nse. when set to ?0? intb is held ?1?.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 71 document id: pmc-2010850, issue 1 register 00ch: nse-8g subsystem interrupt enable register bit type function default bit 31:6 r unused x bit 5 r/w topinte 0 bit 4 r/w csuinte 0 bit 3 r/w r8tdinte 0 bit 2 r/w t8teinte 0 bit 1 r/w ilcinte 0 bit 0 r/w dcbinte 0 this register allows the cpu to disable or enable nse-8g subsystem interrupts with a single write. topinte this bit, when ?1?, enables the generation of interrupts from the top_level i.e. r8c1extraint and r8c1missint interrupts. when set to ?0? r8c1extraint and r8c1missint interrupts are disabled . csuinte this bit, when ?1?, enables the generation of interrupts from csu1 control. when set to ?0? csu1 control interrupts are disabled . r8tdinte this bit, when ?1?, enables the generation of interrupts from r8td blocks. when set to ?0? all r8td interrupts are disabled . t8teinte this bit, when ?1?, enables the generation of interrupts from t8te blocks. when set to ?0? all t8te interrupts are disabled . ilcinte this bit, when ?1?, enables the generation of interrupts from ilc blocks. when set to ?0? all ilc interrupts are disabled . dcbinte this bit, when ?1?, enables the generation of interrupts from the dcb block. when set to ?0? dcb interrupts are disabled .
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 72 document id: pmc-2010850, issue 1 register 00dh: nse-8g r8td tip register bit type function default bit 31:1 r unused x bit 0 r tip 0 this register allows the cpu to determine if the tip signals from all the r8tds are inactive indicating no transfers in progress. tip this bit, when ?1?, indicates one or more of the tip signals from each of the r8tds is active. it is the result of all tip signals ored together.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 73 document id: pmc-2010850, issue 1 register 00eh: sbs user bit 0 bit type function default bit 11:0 r/w sbs_user_0[11:0]* 0 sbs_user_0[n] this bit will be the user 0 bit sent to sbsn over the in-band channel ? where n is any sbs connected to lvds links numbered from 0 to 11*
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 74 document id: pmc-2010850, issue 1 register 00fh: sbs user bit 1 bit type function default bit 11:0 r/w sbs_user_1[11:0]* 0 sbs_user_1[n] this bit will be the user 1 bit sent to sbsn over the in-band channel ? where n is any sbs connected to lvds links numbered from 0 to 11*
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 75 document id: pmc-2010850, issue 1 register 010h: sbs user bit 2 bit type function default bit 11:0 r/w sbs_user_2[11:0]* 0 sbs_user_2[n] this bit will be the user 2 bit sent to sbsn over the in-band channel ? where n is any sbs connected to lvds links numbered from 0 to 11*.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 76 document id: pmc-2010850, issue 1 register 011h: nse-8g free user register bit type function default bit 31:8 r unused x bit 7:0 r/w free[7:0] 0 free[7:0] the software id register (free) holds whatever value is written into it. reset clears the contents of this register. this register has no impact on the operation of the nse.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 77 document id: pmc-2010850, issue 1 register 012h: correct r8td_rx_c1 pulse monitor bit type function default bit 11:0 r r8c1_ok_int[11:0] 0 r8c1_ok_int[n] this bit will be set to ?1? if both oc1fp[n] and r8_rx_c1[n] have occurred at the same time. otherwise, it will be stay at ?0?. read access will clear this bit. section 12.5 describes the proper use of this register.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 78 document id: pmc-2010850, issue 1 register 013h: unexpected r8td_rx_c1 interrupt bit type function default bit 11:0 r r8c1_extra_int[11:0] 0 r8c1_extra_int[n] this bit will be set to ?1? if oc1fp[n] has not occurred at the time when r8_rx_c1[n] has occurred. otherwise, it will stay at ?0?. read access will clear this bit . section 12.5 describes the proper use of this register.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 79 document id: pmc-2010850, issue 1 register 014h: missing r8td_rx_c1 interrupt bit type function default bit 11:0 r r8c1_miss_int[11:0] 0 r8c1_miss_int[n] this bit will be set to ?1? if r8_rx_c1[n] has not occurred at the time when oc1fp[n] has occurred. otherwise, it will stay at ?0?. read access will clear this bit. section 12.5 describes the proper use of this register.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 80 document id: pmc-2010850, issue 1 register 015h: unexpected r8td_rx_c1 interrupt enable bit type function default bit 11:0* r/w r8c1_extra_inte[11:0] 0 r8c1_extra_inte[n] r8c1_extra_inte[n] is used to enable/disable ( ?1? for enable; ?0? for disable) the r8c1_extra_int[n] (defined in reg 013h) to cause interrupt. this is on per channel* basis. *any unused ports must be set to ?0?.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 81 document id: pmc-2010850, issue 1 register 016h: missing r8td_rx_c1 interrupt enable bit type function default bit 11:0* r/w r8c1_miss_inte[11:0]* 0 r8c1_miss_inte[n] r8c1_miss_inte[n] is used to enable/disable ( ?1? for enable; ?0? for disable) the r8c1_miss_int[n] (defined in reg 014h) to cause interrupt. this is on per channel* basis. *any unused ports must be set to ?0?
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 82 document id: pmc-2010850, issue 1 register 020h, 024h: cstr #1 ? 2 control* bit type function default bit 31-16 unused x bit 15 r/w reserved[11] 0 bit 14 r/w reserved[10] 0 bit 13 r/w reserved[9] 0 bit 12 r/w reserved[8] 0 bit 11 r/w reserved[7] 0 bit 10 r/w reserved[6] 1 bit 9 r/w reserved[5] 0 bit 8 r/w reserved[4] 0 bit 7 r/w reserved[3] 0 bit 6 r/w reserved[2] 0 bit 5 r/w reserved[1] 0 bit 4 r/w csu_enb 0 bit 3 r/w csu_rstb 1 bit 2 unused x bit 1 unused x bit 0 r/w reserved[0] 1 this register provides reset control and enable control for cstr block #1 reserved[11:0] the reserved bits must be set to the indicated default value for correct operation of the nse. csu_rstb the csu_rstb signal is a software reset signal that forces the csu into reset. the csu is reset when the csu_rstb is logic 0. the csu is also reset by the nse-8g master analog reset signal. when the csu is reset, the reset signal should be held for at least 100us. csu_enb the csu enable control signal (csu_enb) bit forces the csu into low power configuration. the csu is disabled when csu_enb is logic one. the csu is enabled when csu_enb is logic 0.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 83 document id: pmc-2010850, issue 1 register 021h, 025h: cstr #1 ? 2* interrupt enable and csu lock status bit type function default bit 31-2 r unused x bit 1 r lockv x bit 0 r/w locke 0 this register configures the operation of cstr block #1. locke the csu lock interrupt enable bit (locke) controls the contribution of csu lock state interrupts by the cstr to the device interrupt intb. when locke is high, intb is asserted low when the csu lock state changes. interrupts due to csu lock state are masked when locke is set low. lockv the csu lock status bit (lockv) indicates whether the clock synthesis unit has successfully locked with the system clock. lockv is set low when the csu has not successfully locked with the reference clock. lockv is set high if when the csu has locked with the reference clock.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 84 document id: pmc-2010850, issue 1 register 022h, 026h: cstr #1 ? 2* interrupt indication bit type function default bit 31-1 r unused x bit 0 r locki x locki the csu lock interrupt status bit (locki) reports and acknowledges changes in the csu lock state. locki is set high when the csu achieves lock with the reference clock or loses its lock to the reference clock. locki is cleared on a read to this register when wcimode is logic 0. locki is cleared on a write (of any value) to this register when wcimode is logic one. intb is asserted low when both locke and locki are high. if locke is asserted, locki must be cleared before intb will be reasserted.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 85 document id: pmc-2010850, issue 1 register 044h: dcb configuration port 11-6 register bit type function default bit 31-30 r unused x bit 29-25 r/w port11[4:0] 0 bit 24-20 r/w port10[4:0] 0 bit 19-15 r/w port9[4:0] 0 bit 14-10 r/w port8[4:0] 0 bit 9-5 r/w port7[4:0] 0 bit 4-0 r/w port6[4:0] 0 port11[4:0] this register selects the input port number to map to output port 11 of the dcb for an arbitrary position in the sbi336/telecombus frame. port10[4:0] this register selects the input port number to map to output port 10 of the dcb for an arbitrary position in the sbi336/telecombus frame. port9[4:0] this register selects the input port number to map to output port 9 of the dcb for an arbitrary position in the sbi336/telecombus frame. port8[4:0] this register selects the input port number to map to output port 8 of the dcb for an arbitrary position in the sbi336/telecombus frame. port7[4:0] this register selects the input port number to map to output port 7 of the dcb for an arbitrary position in the sbi336/telecombus frame. port6[4:0] this register selects the input port number to map to output port 6 of the dcb for an arbitrary position in the sbi336/telecombus frame.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 86 document id: pmc-2010850, issue 1 register 045h: dcb configuration port 5-0 register bit type function default bit 31-30 r unused x bit 29-25 r/w port5[4:0] 0 bit 24-20 r/w port4[4:0] 0 bit 19-15 r/w port3[4:0] 0 bit 14-10 r/w port2[4:0] 0 bit 9-5 r/w port1[4:0] 0 bit 4-0 r/w port0[4:0] 0 port5[4:0] this register selects the input port number to map to output port 5 of the dcb for an arbitrary position in the sbi336/telecombus frame. port4[4:0] this register selects the input port number to map to output port 4 of the dcb for an arbitrary position in the sbi336/telecombus frame. port3[4:0] this register selects the input port number to map to output port 3 of the dcb for an arbitrary position in the sbi336/telecombus frame. port2[4:0] this register selects the input port number to map to output port 2 of the dcb for an arbitrary position in the sbi336/telecombus frame. port1[4:0] this register selects the input port number to map to output port 1 of the dcb for an arbitrary position in the sbi336/telecombus frame. port0[4:0] this register selects the input port number to map to output port 0 of the dcb for an arbitrary position in the sbi336/telecombus frame.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 87 document id: pmc-2010850, issue 1 register 046h: dcb configuration output register. bit type function default bit 31-30 r unused x bit 29-0 r cfg_o[29:0] 0 cfg_o[29:0] this field contains configuration data read from the offline connection memory page. configuration data in this field is read from the location specified by the wordaddr and portaddr fields in the access mode register. there is a 6 sysclk cycle latency from when an indirect read is requested until when correct data appears in this register.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 88 document id: pmc-2010850, issue 1 register 047h: dcb access mode register bit type function default bit 31 r/w wrb 1 bit 30 r/w accmde 0 bit 29 r unused x bit 28-24 r/w portcfg[4:0] 0 bit 23-21 r unused x bit 20-16 r/w portaddr[4:0] 0 bit 15-14 r unused x bit 13-0 r/w wordaddr [13:0] 0 writing to this register with the wrb register bit set high initiates an indirect read from the offline connection memory page. wordaddr selects the offline connection memory page to read from. there is a latency of 6 sysclk cycles from when this register is written to with the wrb bit set high until when valid data appears on the configuration output register. indirect reads should be spaced at least 6 sysclk cycles apart to permit valid data to appear in the configuration output register. writing to this register with the wrb register bit set low initiates an indirect write to the offline connection memory page. wordaddr selects the offline connection memory page to write to. indirect writes should be spaced at least 4 sysclk cycles apart to ensure the writes complete successfully. while page copy is in progress (updatev register bit = ?1?), writing to this register will not cause data to be updated to/from the offline connection memory page. while a page swap is pending (swapv register bit = ?1?), writing to this register may cause unpredictable results as data may be transferred while a page swap is occurring, causing data to be updated to a different connection memory page from the intended. wrb the indirect access control bit selects between a write (0) or read (1) access to the offline connection memory page. accmde these bits indicate the access mode of the offline connection memory page. 0 : port transfer mode. 1 : word transfer mode.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 89 document id: pmc-2010850, issue 1 in port transfer mode, one port is updated per word of the offline connection memory page. portcfg: new port mapping to be updated to the connection memory page. wordaddr: specifies the address of the offline connection memory page. portaddr: port address of the offline connection memory page. in word transfer mode, an entire word of the offline connection memory page is updated. portcfg: is ignored. wordaddr: specifies the address to the offline connection memory page. portaddr: is ignored. in either mode, the contents read from the off-line connection memory page can be read by the microprocessor through the configuration output register.. portcfg[4:0] this field contains the input port mapping to a particular output port specified in portaddr. used only in port transfer mode. at all other modes, this field is ignored. portaddr[4:0] when performing writes to the offline connection memory page, this field indicates the output port to be updated with new mapping in portcfg. a portaddr of 0 relates to output port 0 of the dcb. this field is valid in port transfer mode and during reading from the configuration output register and is ignored in word transfer mode. valid values are 0-31 when performing writes. when performing reads through the configuration output register, portaddr indicates the ports being read as follows: 000xx : ports 5-0 001xx : ports 11-6 010xx : ports 17-12 011xx : ports 23-18 100xx : ports 29-24
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 90 document id: pmc-2010850, issue 1 101xx : ports 31-30 on least significant bits 110xx : ports 5-0 111xx : ports 5-0 wordaddr[13:0] this field indicates the address of the update connection memory page to be accessed. this field relates to the time location within the sbi/telecombus frame. i.e. location 0 would be the first a1 byte of the frame and location 24 is the c1 character. this field is ignored in page copy mode. valid values are 0-9719.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 91 document id: pmc-2010850, issue 1 register 048h: dcb c1 delay (rc1dly) register. bit type function default bit 31-6 r unused x bit 13-0 r/w rc1dly[13:0] 0 rc1dly this value, equaling the delay (in 77.76 mhz clock periods), between rc1fp and the arrival of the c1 characters in the r8td. this delay will synchronize the c1 input to the r8td blocks assuming all the c1 characters have arrived. as the delay on those links is dependent on the system design, backplane propagation delays, cable lengths etc. this value will have to be arrived at empirically. and will have an upper an lower limit for which the middle value should be selected. the operations section for more detail and some recommended starting values. mf_swap legal range (clock cycles) 00 26 ? 9716 01 26 ? 16383 10 26 ? 16383 11 26 ? 16383
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 92 document id: pmc-2010850, issue 1 register 04ah: dcb frame size register bit type function default bit 31-14 r unused x bit 13-0 r/w frmsz[13:0] 9719 this register specifies the frame size of the sbi or telecombus frame. frmsz[13:0] this register specifies the size of the connection memory page in the various switching modes. legal values: 1079: telecombus switching. 1079: sbi column switching. 9719: sbi ds0 switching. 9719: sbi ds0 switching with cas.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 93 document id: pmc-2010850, issue 1 register 04ch: dcb configuration register bit type function default bit 31- 8 r unused x bit 7-6 r/w mf_swap[1:0] 0 bit 5 r/w auto 0 bit 4 r/w swap_pe 0 bit 3 r/w updatee 0 bit 2 r/w framee 0 bit 1 r swappv 0 bit 0 r updatev 0 mf_swap [1:0] this bit selects when rc1fp is expected and synchronizes when page swaps can occur. table below relates mfswap to all vital variables from the dcb: mfswap configuration page size frame switching @ (9720 byte frame) frame interrupt rc1fp expected every switching mode 00 1080 1 frame 1 frame 4 frame telecombus 01 1080 4 frame 4 frame 4 frame sbi column mode 10 9720 4 frame 4 frame 4 frame sbi ds0 mode 11 9720 48 frame 48 frame 48 frame sbi ds0 with cas auto this bit enables an automatic copy of the online connection memory page to the offline connection memory page after the connection memory page is switched. t oggling the auto bit to ?0? while a page copy is in progress will terminate the page copy process. 0: automatic update disabled. 1: automatic update enabled. if automatic page copying is used, the page copy will take place automatically whenever the connection memory page swaps. this means that the updatev register bit will be asserted immediately following a change from 1 to 0 in the swapv register bit. when the auto bit is set, access to the offline connection memory page is restricted from when a page swap is pending until when the page copy is complete . swap_pe this bit enables the propagation of interrupt to the int output due to a change in state of swapv. this bit does not have an impact on swapi bit.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 94 document id: pmc-2010850, issue 1 0: disables interrupt propagation to the int output. 1: enables interrupt propagation to the int output. updatee this bit enables the propagation of interrupt to the int output when updatev changes state from 1 to 0. this bit does not have impact on updatei bit 0: disables interrupt propagation to the int output. 1: enables interrupt propagation to the int output. framee this bit enables the propagation of interrupt to the int output when cmp is sampled at the expected rc1fp position. this bit does not have an impact on framei bit. 0: disables interrupt propagation to the int output. 1: enables interrupt propagation to the int output. swapv the swapv bit contains the current state of the page swap. this bit is logic one when a switch to the connection memory page (cmp) input has been recognized but the page swap has not yet happened. this bit is a logic 0 when page swap is not pending. when a page swap is pending, writing to the offline page or initiating a page copy may cause corruption of the memory pages. updatev: this bit is updated when the active connection memory page is copied to the offline connection memory page. 0: copying completed. 1: copying in progress. the duration of a page copy is highly dependent on mf_swap. mf_swap sysclk clock cycles required ?00? 1083
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 95 document id: pmc-2010850, issue 1 ?01? 1083 ?10? 9723 ?11? 9723 when a page copy is in progress, attempting to write to the offline connection memory page will be ignored and attempting to read from the offline connection memory page will return unpredictable results.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 96 document id: pmc-2010850, issue 1 register 04dh: dcb interrupt status register. bit type function default bit 31-3 x unused 0 bit 2 i swapi x bit 1 i updatei x bit 0 i framei x writing to this register initiates copying of the active connection memory page to the offline connection memory page. when a page swap is pending (swapv =?1?) writing to this register may cause a corruption of the connection memory pages. swapi this bit reports and acknowledges a change of state in the swapv bit of the configuration register. this bit is cleared when this register is read. when enabled by swape, the int output reflects the state of this bit. updatei the offline page copy interrupt status bit, updatei reports and acknowledges a change of state from 1 to 0 in the updatev bit of the configuration register. this signifies that a page copy is complete. this bit is cleared when read. when enabled by the updatee bit, the int output reflects the state of this bit. framei the frame interrupt status bit reports the sampling of the cmp bit at the expected rc1fp position. when enabled by framee, frequency of occurrence of framei is dependent on mf_swap. when enabled by the framee bit, the int output reflects the state of this bit. mf_swap framei occurs every 00 1 frame 01 4 frame 10 4 frame 11 48 frame this bit is cleared when read. a change in the cmp input should be sequenced to occur as soon as possible after the occurrence of framei. changing cmp prior to the occurrence of framei may cause unpredictable behavior as it may cause cmp to be sampled later than expected.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 97 document id: pmc-2010850, issue 1 register 100h + n*20h, r8td control and status bit type function default bit 31:16 r unused x bit 15 r/w reserved[1] 0 bit 14 r/w reserved[0] 0 bit 13:10 r unused x bit 9 r/w rxinv 0 bit 8 r/w reserved[2] 0 bit 7 r/w fuoe 0 bit 6 r/w lcve 0 bit 5 r/w ofae 0 bit 4 r/w ocae 0 bit 3 r ofav x bit 2 r ocav x bit 1 r/w fofa 0 bit 0 r/w foca 0 this register provides control and reports the status of the r8td blocks. foca the force out-of-character-alignment bit (foca) control the operation of the character alignment block in the r8td block. a 0-1 transition on this bit forces the character alignment block to the out-of-character-alignment state where it will search for the transport frame alignment character (k28.5). before another force operation can be performed, foca must first be set to logic 0. fofa the force out-of-frame-alignment bit (fofa) controls the operation of the frame alignment block in the r8td block. a 0-1 transition on this bit forces the frame alignment block to the out-of-frame-alignment state where it will search for the transport frame alignment character (k28.5). before another force operation can be performed, fofa must first be set to logic 0. ocav the out-of-character-alignment status bit (ocav) reports the state of the character alignment block in the r8td block. ocav is set high when the character alignment block is in the out- of-character-alignment state. ocav is set low when the character alignment block is in the in-character-alignment state.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 98 document id: pmc-2010850, issue 1 ofav the out-of-frame-alignment status bit (ofav) reports the state of the frame alignment block in the r8td block. ofav is set high when the frame alignment block is in the out-of-frame- alignment state. ofav is set low when the frame alignment block is in the in-frame- alignment state. ocae the out of character alignment interrupt enable bit (ocae) masks the contribution of the change of character alignment event indication bit (ocai) in the r8td block to intb. when ocae is high, intb is asserted low when ocai is high. intb is not affected by the value of ocai when ocae is low. ofae the out of frame alignment interrupt enable bit (ofae) masks the contribution of the change of frame alignment event indication bit (ofai) in the r8td block to intb. when ofae is high, intb is asserted low when ofai is high. intb is not affected by the value of ofai when ofae is low. lcve the line code violation interrupt enable bit (lcve) masks the contribution of the line code violation event indication bit (lcvi) in the r8td block to intb. when lcve is high, intb is asserted low when lcvi is high. intb is not affected by the value of lcvi when lcve is low. fuoe the fifo underrun/overrun status interrupt enable bit (fuoe) masks the contribution of the fifo underrun/overrun event indication bit (fuoi) in the r8td block to intb. when fuoe is high, intb is asserted low when fuoi is high. intb is not affected by the value of fuoi when fuoe is low. rxinv the receive data invert bit (rxinv) controls the active polarity of the incoming data stream. when rxinv is set high, the data is complemented before any processing by the r8td. when rxinv is set low, data is not complemented before r8td processing. reserved[2:0] the reserved[2:0] bits must be set to the indicated default value for correct operation of the nse.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 99 document id: pmc-2010850, issue 1 register 101h + n*20h, r8td interrupt status bit type function default bit 31:8 unused x bit 7 r fuoi x bit 6 r lcvi x bit 5 r ofai x bit 4 r ocai x bit 3:0 unused x these registers reports interrupt status due to change of character alignment events and detection of line code violations for the r8td block. ocai the out-of-character-alignment interrupt status bit (ocai) reports and acknowledges change of character alignment state events for the r8td block. ocai is set high when the character alignment block changes state to the out-of-character-alignment state or to the in-character- alignment state since the last clear for the register. ocai is cleared on a read to this register when wcimode is logic 0. ocai is cleared on a write (of any value) to this register when wcimode is logic one. intb is asserted low when both ocae and ocai are high. if ocae is asserted, ocai must be cleared before intb will be reasserted. ofai the out-of-frame-alignment interrupt status bit (ofai) reports and acknowledges change of frame alignment state events for the r8td block. ofai is set high when the frame alignment block changes state to the out-of-frame-alignment state or to the in-frame-alignment state. ofai is cleared on a read to this register when wcimode is logic 0. ofai is cleared on a write (of any value) to this register when wcimode is logic one. intb is asserted low when both ofae and ofai are high. if ofae is asserted, ofai must be cleared before intb will be reasserted. lcvi the line code violation event interrupt status bit (lcvi) reports and acknowledges line code violation events for the r8td block. lcvi is set high when the character alignment block detects a line code violation in the incoming data stream. lcvi is cleared on a read to this register when wcimode is logic 0. lcvi is cleared on a write (of any value) to this register when wcimode is logic one. intb is asserted low when both lcve and lcvi are high. if lcve is asserted, lcvi must be cleared before intb will be reasserted.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 100 document id: pmc-2010850, issue 1 fuoi the fifo underrun/overrun event interrupt status bit (fuoi) reports and acknowledges the fifo underrun/overrun events for the r8td block. fuoi is set high when r8td detects a that the fifo read and write pointers are within one slot of each other. fuoi is cleared on a read to this register when wcimode is logic 0. fuoi is cleared on a write (of any value) to this register when wcimode is logic one. intb is asserted low when both fuoe and fuoi are high. if fuoe is asserted, fuoi must be cleared before intb will be reasserted.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 101 document id: pmc-2010850, issue 1 register 102h + n*20h, r8td line code violation count bit type function default bit 31:16 unused x bit 15:0 r lcv[15:0] x these registers reports the number of line code violations in the previous accumulation period for the r8td blocks. lcv[15:0] the lcv[15:0] bits reports the number of line code violations that have been detected since the last time the lcv registers were polled. the lcv registers are polled by writing to the tip register or by writing to this register. within 10 us of either event, the internally accumulated error count is transferred to the lcv registers and the internal error counter is simultaneously reset to begin a new cycle of error accumulation.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 102 document id: pmc-2010850, issue 1 register 103h + n*20h, rxlv and dru control bit type function default bit 31:16 r unused x bit 15 r/w dru_dtmsb 1 bit 14 r/w reserved 1 bit 13 r/w dru_enb 0 bit 12 r/w rx_enb 0 bit 11 r/w reserved 0 bit 10 r/w a_rstb 1 bit 9 r/w reserved[4] 0 bit 8 r/w reserved[3] 0 bit 7 r/w reserved[2] 0 bit 6 r/w reserved[1] 0 bit 5 r/w dru_ctrl[3] 0 bit 4 r/w dru_ctrl[2] 0 bit 3 r/w dru_ctrl[1] 0 bit 2 r/w dru_ctrl[0] 0 bit 1 r/w reserved[0] 0 bit 0 unused x these registers drives the control signals for the rxlv and dru blocks. after chip reset, this register must be set to cc34h for proper operation, see below. dru_ctrl[3:0] the dru_ctrl[3:0] bits control the dru ctrl[3:0] inputs. the dru_ctrl[3:0] bus is reset to 0000, but needs to be set to 1101 following a reset for correct operation of the nse. a_rstb the a_rstb bit is a soft-reset for the data recovery unit analog block. setting a_rstb to logic 0 will reset the block. reserved the reserved bit is set to logic 0 on reset, but needs to be set to logic one following reset for correct operation of the nse.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 103 document id: pmc-2010850, issue 1 rx_enb the rxlv enable bit (rx_enb) bit controls the operation of rxlv block #x. setting rx_enb to logic 0 enables the block. setting rx_enb to logic one disables the block. dru_enb the dru enable bit (dru_enb) bit controls the operation of data recovery unit analog block #x. setting dru_enb to logic 0 enables the block. setting dru_enb to logic one disables the block.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 104 document id: pmc-2010850, issue 1 register 108h + n*20h, t8te control and status bit type function default bit 31:6 unused x bit 5 r/w reserved[1] 0 bit 4 r/w fifoerre 0 bit 3 r/w tpins 0 bit 2 r/w reserved[0] 0 bit 1 w center 1 bit 0 r/w dlcv 0 these registers provide, control and report the status of the t8te blocks. reserved[1:0] the reserved bit must be set to the indicated default value for correct operation of the nse. dlcv the diagnose line code violation bit (dlcv) controls the insertion of line code violation in the outgoing data stream. while dlcv is logic one and tcbmode is logic 0, the transmitted 8b/10b codes are inverted. this will result in at least one disparity error at a receive 8b/10b decoder. when the nse-8g is configured with tcbmode logic one, and dlcv logic one, 8b/10b data characters are inverted while the telecombus control characters are not inverted. when dlcv is logic 0, no code inversion is performed. center the fifo centering control bit (center) controls the separation of the t8te fifo read and write pointers. center is a write only bit. when a logic high is written to center, and the current fifo depth is not in the range of 3, 4 or 5 characters, the fifo depth is forced to be four 8b/10b characters deep, with a momentary data corruption. writing to the center bit when the fifo depth is in the 3, 4 or 5 character range produces no effect. center always returns a logic low when read. this bit must be set after csu lock has been achieved to properly center the fifo. tpins the test pattern insertion (tpins) controls the insertion of test pattern in the outgoing data stream for jitter testing purpose. when this bit is set high, tp[9:0] in the t8te test pattern register is selected for output.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 105 document id: pmc-2010850, issue 1 fifoerre the fifo underrun/overrun error interrupt enable bit (fifoerre) masks the contribution of the fifo underrun/overrun event indication bit (fifoerri) in the t8te block to intb. when fifoerre is high, intb is asserted low when fifoerri is high. intb is not affected by the value of fifoerri when fifoerre is low.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 106 document id: pmc-2010850, issue 1 register 109h + n*20h, t8te interrupt status bit type function default bit 31:5 unused x bit 4 r fifoerri 0 bit 3:0 unused x these registers report the interrupt status for t8te blocks #0 through #11. fifoerri the fifo overrun/underrun error interrupt indication bit (fifoerri) reports a fifo overrun/underrun error event. fifoerri is set high when when fifo logic detects fifo read and write pointers in close proximity to each other. fifoerri is cleared on a read to this register when wcimode is logic 0. fifoerri is cleared on a write (of any value) to this register when wcimode is logic one. intb is asserted low when both fifoerre and fifoerri are high. if fifoerre is asserted, fifoerri must be cleared before intb will be reasserted.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 107 document id: pmc-2010850, issue 1 register 10ah + n*20h: t8te time-slot configuration #1 bit type function default bit 31:16 r unused x bit 15 r/w tmode8[1] 0 bit 14 r/w tmode8[0] 0 bit 13 r/w tmode7[1] 0 bit 12 r/w tmode7[0] 0 bit 11 r/w tmode6[1] 0 bit 10 r/w tmode6[0] 0 bit 9 r/w tmode5[1] 0 bit 8 r/w tmode5[0] 0 bit 7 r/w tmode4[1] 0 bit 6 r/w tmode4[0] 0 bit 5 r/w tmode3[1] 0 bit 4 r/w tmode3[0] 0 bit 3 r/w tmode2[1] 0 bit 2 r/w tmode2[0] 0 bit 1 r/w tmode1[1] 0 bit 0 r/w tmode1[0] 0 register 02h configures the path termination mode of time-slots 1 to 8 of the t8te. tmode1[1:0]-tmode8[1:0] the time-slot path termination mode select register bits (tmode1[1:0]-tmode8[1:0]) configures the mode settings for time-slots 1 to 8 of the t8te. time-slots are numbered in order of transmission in the incoming telecombus stream (id[7:0]). time-slot #1 is the first byte transmitted and time-slot #12 is the last byte transmitted. the setting stored in tmodex[1:0] (x can be 1-12) determines which set of telecombus control signals are to be encoded in 8b/10b characters. in telecombus mode, the t8te encodes telecombus control signals such as transport frame and payload boundaries, pointer justification events and alarm conditions into three levels of an extended set of 8b/10b characters as well as performing the ieee mode conversion on data. the two hierarchical levels are high-order path termination (hpt) and low-order path termination (lpt). for correct operation see table below: tmodex[1] tmodex[0] mode functional description 0 0 reserved invalid 01hpt level use for telecombus where v1/v2 pointers must be preserved 10lpt level use for sbi336s or telecombus with valid v5 but without valid v1/v2 pointers 1 1 reserved invalid
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 108 document id: pmc-2010850, issue 1 register 10bh + n*20h: t8te time-slot configuration #2 bit type function default bit 31:8 unused x bit 7 r/w tmode12[1] 0 bit 6 r/w tmode12[0] 0 bit 5 r/w tmode11[1] 0 bit 4 r/w tmode11[0] 0 bit 3 r/w tmode10[1] 0 bit 2 r/w tmode10[0] 0 bit 1 r/w tmode9[1] 0 bit 0 r/w tmode9[0] 0 register 03h configures the path termination mode of time-slots 9 to 12 of the t8te. tmode9[1:0]-tmode12[1:0] the time-slot path termination mode select register bits (tmode9[1:0]-tmode12[1:0]) configures the mode settings for time-slots 9 to 12 of the t8te. time-slots are numbered in order of transmission in the incoming telecombus stream (id[7:0]). time-slot #1 is the first byte transmitted and time-slot #12 is the last byte transmitted. the setting stored in tmodex[1:0] (x can be 1-12) determines which set of telecombus control signals are to be encoded in 8b/10b characters. in telecombus mode, the t8te encodes telecombus control signals such as transport frame and payload boundaries, pointer justification events and alarm conditions into three levels of an extended set of 8b/10b characters as well as performing the ieee mode conversion on data. the two hierarchical levels are high-order path termination (hpt) and low-order path termination (lpt). for correct operation see the table below: tmodex[1] tmodex[0] mode functional description 0 0 reserved invalid 0 1 hpt level use for telecombus where v1/v2 pointers must be preserved 1 0 lpt level use for sbi336s or telecombus with valid v5 but without valid v1/v2 pointers 1 1 reserved invalid
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 109 document id: pmc-2010850, issue 1 register 10ch + n*20h, t8te test pattern bit type function default bit 31:10 unused x bit 9 r/w tp[9] 1 bit 8 r/w tp[8] 0 bit 7 r/w tp[7] 1 bit 6 r/w tp[6] 0 bit 5 r/w tp[5] 1 bit 4 r/w tp[4] 0 bit 3 r/w tp[3] 1 bit 2 r/w tp[2] 0 bit 1 r/w tp[1] 1 bit 0 r/w tp[0] 0 these registers store the test pattern for test pattern insertion for the t8te blocks. tp[9:0] the test pattern register (tp[9:0]) for t8te block #x contains the test pattern conditionally inserted into output data stream #x. tp[9:0] is inserted into the output data stream when the tpins bit is set high.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 110 document id: pmc-2010850, issue 1 register 10dh + n*20h, txlv and piso control bit type function default bit 31:12 unused x bit 11 reserved[8] 0 bit 10 r/w reserved[7] 0 bit 9 r/w reserved[6] 0 bit 8 r/w txlv_enb 0 bit 7 r/w piso_enb 0 bit 6 r/w reserved[5] 0 bit 5 r/w reserved[4] 0 bit 4 r/w reserved[3] 0 bit 3 r/w reserved[2] 0 bit 2 r/w reserved[1] 1 bit 1 r/w reserved[0] 1 bit 0 r/w arstb 1 arstb the analog reset bit (arstb) resets the associated txlv and piso blocks. when arstb is set to logic 0, the txlv and piso are reset. reserved[5:0] the reserved[3:0] bits must be set to the indicated default value for correct operation of the nse. piso_enb the piso enable bit (piso_enb) controls the operation of the piso block. piso_enb is set to logic one to disable the piso block. piso_enb is set to logic 0 to enable the piso block. txlv_enb the txlv enable bit (txlv_enb) controls the operation of txlv block. txlv_enb is set to logic one to disable the txlv block. txlv_enb is set to logic 0 to enable the txlv block. reserved[8] the reserved[8] bit must be set to the indicated default value for correct operation of the nse.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 111 document id: pmc-2010850, issue 1 register 110h + n*20h, ilc transmit fifo data bit type function default bit 31-0 r/w tdat[31:0] 0 tdat[31:0] tdat[31: 0]transmit fifo form the 32 bit wide data word to be written to the register file fifo. a single 32 bit write to this register will update tdat[31:0]. a write to this address initiates a fifo write sequence.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 112 document id: pmc-2010850, issue 1 register 111h + n*20h, ilc transmit control register bit type function default bit 31:16 unused x bit 15:8 r/w tx_aux[7:0] 00000000 bit 7:6 r reserved 00 bit 5:4 r/w tx_link[1:0] 00 bit 3:2 r reserved 00 bit 1 r/w tx_crc_swiz_en 0 bit 0 r/w tx_bypass 0 tx_bypass when this bit is set to ?1?, the blocks message transmit functions are bypassed. no messages are inserted into the transmit bus data the respective signals are passed through the block?s pipeline unmodified. transmit message fifo ram is disabled and thus message data writes are ignored. tx_crc_swiz_en when this bit is set to ?1?, the calculated crc-16 is bit reversed before being transmitted. this facility can be used for diagnostic testing of crc-16 generation and checking functionality. tx_link[1:0] these bits are transmitted in the link bits of the message header of the next available message. on reads these bit return the last written value. tx_aux[7:0] these bits form the input to an auxiliary channel between cpus at each end of the link. their use is at the software developers? discretion. data written to this register will be transmitted in the aux header byte of each subsequent message to the other end of the inband link. a new value of tx_aux will be transmitted at the next available message. data read from this register will be the data previously written.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 113 document id: pmc-2010850, issue 1 register 112h + n*20h, ilc transmit misc.status and fifo synch register bit type function default bit 31:16 unused x bit 15 r tx_msg_lvl_valid n/a bit 14:13 r tx_link[1:0] 00 bit 12:11 r ipage[1:0] n/a bit 10:8 r iuser[2:0] n/a bit 7:6 r reserved 00 bit 5:2 r tx_msg_lvl[3:0] 0000 bit 1 r tx_fi_busy 0 bit 0 w tx_xfer_sync 0 this register serves a dual purpose dependant on whether it is being read or written. when it is read it returns the status for the message transmit channel. when it is written (with 0001h) to it is used it synchronize the transmit fifo to the start of a message boundary. tx_xfer_sync writing ?1? to this bit initializes the next write sequence to be to the beginning of the next message. after a ?1? had been written successive writes to the transmit fifo will be to location zero of the next available slot. if a partial message has been written, tx_xfer_sync indicates that the current message is complete and that subsequent writes will be to the next message. if more than 32 bytes are written, the 33rd byte will be the first byte of the next message. the purpose of this bit is to unambiguously align the message boundaries. another use would be to abandon the current write and move the write pointer to the beginning of the next message. (previous message data will remain in the unwritten portion of the message being abandoned, which will have to be ignored by the receiving software). if the message fifo pointers are already at a message boundary then writing this bit to a ?1? will have no affect. on reads this bit is always returned as a ?0?. tx_fi_busy this bit indicates that the internal hardware is transferring the data from the transmit fifo registers (tdat) into the internal ram. this bit need not be read by software if the time interval between successive 32 bit transfers is greater than 3 sysclk cycles. user and page bits are a copy of the user bits received, and being transmitted in 0ch. these allow one read in the 32 bit device to gain a snapshot of the entire ilc.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 114 document id: pmc-2010850, issue 1 tx_msg_lvl[3:0] this indicates the current number of messages in the txfifo. table 7 tx fifo message level tx_msg_lvl[3:0] number of messages 0000 0 :: 1000 8 values greater than 1000 will not occur. the number of free messages available in the fifo is given by (8 ? tx_msg_lvl). iuser this bits are a reflection of the iuser[2:0]. these reflect the user bits that will be transmitted in subsequent message headers. there is no default value for these bits as they are device dependant. ipage this bits are a reflection of the ipage[1:0. these reflect the page bits that will be transmitted in subsequent message headers. there is no default value for these bits as they are device dependant. tx_link[1:0] these bits reflect the last written value of the tx_link field of the tx control register. the upper byte of this register therefore reflects all of the configurable bits of the message header1 byte. tx_msg_lvl_valid this bit indicates that the value of tx_msg_lvl is valid. when read with a ?0? this register should be re-read until tx_msg_lvl_valid is a ?1?. this bit will be clear for only approximately 0.3% of time.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 115 document id: pmc-2010850, issue 1 register 113h + n*20h, ilc receive fifo data register bit type function default bit 31:0 r rdat[31:0] 00000000h rdat[31:0] rdat[31: 0] is the 32 bit wide data word read from the fifo. a single read from this register will update rdat[31:0]. a read from this address initiates a fifo read sequence.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 116 document id: pmc-2010850, issue 1 register 114h + n*20h, ilc receive control register bit type function default bit 31:16 unused x bit 15:3 r reserved[15:3] 00000000000000 bit 2 r/w reserved[2] 0 bit 1 r/w rx_crc_swiz_en 0 bit 0 r/w rx_bypass 0 rx_bypass when this bit is set to ?1?, the blocks message receive functions are bypassed. no messages are extracted from the receive telecombus. the rxtpl , rxpl and rxdata signals are passed through the blocks pipeline unmodified. receive message fifo ram is disabled and thus message data reads return undefined data. rx_crc_swiz_en when this bit is set to ?1?, the calculated crc-16 is bit reversed before being compared with crc-16 bytes of the received message. this facility can be used for diagnostic testing of crc-16 generation and checking functionality. reserved[15:3] reserved for future use. reserved[2] default value is ?0?, but should be set to ?1? for correct operation.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 117 document id: pmc-2010850, issue 1 register 115h + n*20h, ilc receive auxiliary, status and fifo synch register bit type function default bit 31:24 r reserved 00000000 bit 23:16 r rx_aux[7:0] 00h bit 15 r rx_stts_valid n/a bit 14:13 r rx_link[1:0] 00 bit 12:11 r rx_page[1:0] 00 bit 10:8 r rx_user[2:0] 000 bit 7 r crc_err 0 bit 6 r hdr_crc_err 0 bit 5:2 r rx_msg_lvl[3:0] 0000 bit 1 r rx_fi_busy 0 bit 0 w rx_xfer_sync n/a bit 0 r rx_sync_done 0 this register serves a dual-purpose dependant on whether it is being read or written. when it is read it returns the status for the message receive channel. when it is written (with 00000001h) to it is used it synchronize the receive fifo to the start of a message boundary or perform a message skip. rx_aux[7:0] these bits constitute the output from an auxiliary channel between cpus at each end of the link. their use is at the software developers? discretion. a read from this register will return the aux header byte of the last message received (without a crc-16 error). rx_xfer_sync rx transfer sync writing writing ?1? to this bit initiates a read sequence from the start of the next unread message. the hardware aligns the message read buffer address to the start of the next unread message prefetches the 1 st dword from the unread message buffer so that it is ready for a s/w read from the receive fifo data register(s) an unread message in this context means that the s/w has not read any of the message payload data by reading the receive fifo data register(s) after the rx xfer sync process has been completed successive reads from the receive fifo return the last dword read from the receive fifo and prefetch the next dword (when available). this bit must be written to a ?1? at the start of a message read sequence.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 118 document id: pmc-2010850, issue 1 when multiple complete messages are being read (software knows that there is more than one message in the fifo using the rx_msg_lvl bits) this bit does not need to be written between individual message reads. it must be written for the 1 st message. when software uses a variable length message protocol it may want to abandon reading a message buffer before reading the entire message buffer of 8 dwords (16 words). in this case this bit must be written with a ?1? to move the message pointer to the start of the next message buffer before starting the read of that buffer. after writing this bit with a ?1? software should not start reading the fifo until the rx_fi_busy bit has cleared. in the worst case this will take 5 sysclk cycles when fast_rd_en = ?1? and 4 sysclk cycles when fast_rd_en = ?0?. at this point the 1 st dword of the message is available for reading and the crc_err bit is valid. software may abandon a crc errored message without reading the message buffer by writing this bit with a ?1? again. on reads this bit is always returns the rx_sync_done status. a suggested s/w procedure for accessing the receive message buffer is outlined in section 12.12.2 (accessing the receive message fifo) rx_sync_done this bit indicates the status of an rx_xfer_sync operation. when ?1? it indicates that an rx_xfer_sync has been done. s/w should check this bit at the start of a message read sequence or when attempting to perform a message skip sequence. rx_fi_busy this bit indicates that the internal hardware is transferring data from the receive fifo ram into the receive fifo registers. the bits is set following a write to the receive fifo synch register (bh) with the rx_xfer_sync bit set. a read from the receive fifo data low register. following an rx_xfer_sync write this bit need not be read by software if the time interval to the successive receive fifo data register read is greater than approximately 5 sysclk cycles when fast_rd_en = ?1? or approximately 4 sysclk cycles when fast_rd_en = ?0?. this bit need not be read by software if the time interval between successive receive fifo data register reads greater than approximately 4 sysclk cycles when fast_rd_en = ?1? or approximately 3 sysclk cycles when fast_rd_en = ?0?.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 119 document id: pmc-2010850, issue 1 rx_msg_lvl[3:0] this indicates the current number of messages in the receive fifo. table 8 rx fifo message level rx_msg_lvl[3:0] number of messages 0000 0 :: 1000 8 values greater than 1000 will not occur. hdr_crc_err if this bit is set to ?1?, the last message slot received was received with an errored crc-16 field. this bits is updated every message slot. this bit is provided as status only. crc_err if this bit it set to ?1?, the message at the head of the receive fifo has an errored crc-16 field. the usual sequence would be to read this register before reading the message buffer to check if the message buffer that will be read from next has been received with a crc error. if a receive fifo synchronization has been started the value of this bit is invalid until the rx_xfer_sync operation has completed. when fast_rd_en is a ?1? this bit is valid when rx_fi_busy is a ?0? following a receive fifo synchronization. when fast_rd_en is a ?0? the values of rx_fi_busy and crc_err change concurrently and a further read should be made after rx_fi_busy is sampled as a ?0? before checking the value of this bit. ouser[2:0] these bits are a reflection of the ouser[2:0] bits output from the far end and indicate the value of the received user bits in the received message header of the last message received (without a crc-16 error). these bits are available in the three top level sbs user bits registers at a bit position equal to the link number. opage[1:0] these bits are a reflection of the opage[1:0] bits output from the far end and indicate the value of the received page bits in the received message header of the last message received (without a crc-16 error). these bits are available in the two top level sbs page bits registers at a bit position equal to the link number.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 120 document id: pmc-2010850, issue 1 rx_link[1:0] these bits indicate the value of the link bits from the message header of the last message received (without a crc-16 error). rx_stts_valid this bit indicates that the values of rx_msg_lvl , rx_link, opage, ouser are valid. in 32 bit mode this bit also indicates whether the value of rx_aux (returned in bits 16 to 23) is valid. when read with a ?0? this register should be re-read until rx_stts_valid is a ?1?. this bit will be set for only approximately 0.15% of time.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 121 document id: pmc-2010850, issue 1 register 116h + n*20h, ilc interrupt enable and control register bit type function default bit 31:16 unused x bit 15:13 r reserved 000 bit 12:11 r/w rx_timeout_val[1:0] 00 bit 10:8 r/w rx_threshold_val[2:0] 101 bit 7 r reserved 0 bit 6 r/w rx_timeoute 0 bit 5 r/w rx_thrshlde 0 bit 4 r/w rx_ovflwe 0 bit 3 r/w rx_link_chge 0 bit 2:1 r/w rx_page_chge[1:0] 0 bit 0 r/w rx_user0_chge 0 rx_user0_chge writing a ?1? to the rx_ouser0_chge bit enables the generation of an interrupt on a change of state from a ?0? to a ?1? of received message header bit rx_user[0]. rx_page_chge[1:0] writing a ?1? to the rx_page_chge[n] bit enables the generation of an interrupt on a change of state of the received page bits. the rx_page bits that changed value are indicated by a ?1? in the corresponding rx_page_chgi[n]. rx_link_chge writing a ?1? to the rx_link_chge bit enables the generation of an interrupt on a change of state of the received link bits. when either of the received link bits has changed value the rx_link_chgi bit will be set to a ?1?. if the rxfifo level had reached the threshold value an interrupt will be generated if this bit is ?1?. to disable set to ?0?. rx_ovflwe writing a ?1? to the rx_ovflwe bit enables the generation of an interrupt when rx_ovflwi is a ?1?. rx_thrshlde writing a ?1? to the rx_thrshlde bit enables the generation of an interrupt when rx_thrshldi is a ?1?
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 122 document id: pmc-2010850, issue 1 rx_timeoute writing a ?1? to the rx_timeoute bit enables the generation of an interrupt when rx_timeouti is a ?1? rx_thrshld_val[2:0] variable threshold dictates the minimum number of messages required to be in the rxfifo before an interrupt is generated. ?000? = 1 message ?111? = 8 messages. table 9 rxfifo threshold values rx_thrshld_val [2:0] messages 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 if the rxfifo has not been read for the amount of time indicated by the rxfifo_timeout_delay and the fifo is not empty an interrupt will be generated if this bit is ?1?. to disable set to ?0?. if the rxfifo overflows an interrupt will be generated if this bit is ?1?. to disable set to ?0?. if the rx message fails its crc check, an interrupt will be generated if this bit is ?1?. to disable set to ?0?. rx_timeout_val these bits specify a variable delay, relative to a read from the receive message fifo, in steps of 125 us, before an interrupt is generated, if the receive fifo level is greater than 0. the objective is to stop stale messages collecting in the rxfifo.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 123 document id: pmc-2010850, issue 1 table 10 rxfifo timeout delay rx_timeout_val[1:0] nominal delay in frames minimum delay from message reception maximum delay from message reception minimum delay from fifo read maximum delay from fifo read 00 1 152us 222 us 125us 250 us 01 2 277us 347 us 250us 375us 10 3 402us 472 us 375us 500us 11 4 527us 597 us 500us 625 us
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 124 document id: pmc-2010850, issue 1 register 117h + n*20h: ilc interrupt reason register bit type function default bit 31:0 unused x bit 15:7 r reserved 000000000 bit 6 r rx_timeouti 0 bit 5 r rx_thrshldi 0 bit 4 r rx_ovflwi 0 bit 3 r rx_link_chgi 0 bit 2:1 r rx_page_chgi[1:0] 0 bit 0 r rx_ouser0_chgi 0 this register contains the status of events that may be enabled to generate interrupts. all bits in this register are cleared on read rx_ouser0_chgi a ?1? in this bit indicates that the last received value of the rx_user[0] header bit has changed from a ?0? to a ?1? from the previously received values. this bit is cleared on a read. rx_page_chgi [1:0] a ?1? in these bits indicates that the last received value of the corresponding rx_page[1:0] header bits has changed from the previously received values. these bits are cleared on read. rx_link_chgi a ?1? in this bit indicates that the last received value of the link[1:0] header bits has changed from the previously received values. this bit is cleared on a read. rx_ovflwi this bit, when ?1?, indicates a receive fifo overflow. this bit is cleared on a read. rx_thrshldi this bit, when ?1?, indicates a receive fifo threshold reached. this bit is cleared on a read. rx_timeouti this bit, when ?1?, indicates a receive fifo timeout. this bit is cleared on read.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 125 document id: pmc-2010850, issue 1 11 test features description the test mode registers, shown in table 11, are used for production and board testing. during production testing, the test mode registers are used to apply test vectors. in this case, the test mode registers (as opposed to the normal mode registers) are selected when a[10] is high. during board testing, the digital output pins and the data bus are held in a high-impedance state by simultaneously asserting (low) the csb, rdb, and wrb inputs. all of the tsbs for the nse- 8g are placed in test mode 0 so that device inputs may be read and device outputs may be forced through the microprocessor interface. note: the nse-8g supports a standard ieee 1149.1 five-signal jtag boundary scan test port that can be used for board testing. all digital device inputs may be read and all digital device outputs may be forced through this jtag test port. table 11 test mode register memory map address register 000h-7ffh normal mode registers 800h master test register 801h ? fffh reserved for test 11.1 master test and test configuration registers notes on test mode register bits 1. writing values into unused register bits has no effect. however, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. 2. writeable test mode register bits are not initialized upon reset unless otherwise noted.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 126 document id: pmc-2010850, issue 1 register 800h: nse-8g master test bit type function default bit 31:6 r unused x bit 5 w pmcatst x bit 4 w pmctst x bit 3 w dbctrl 0 bit 2 r/w iotst 0 bit 1 w hizdata 0 bit 0 r/w hizio 0 this register is used to enable nse-8g test features. all bits, except pmctst, and pmcatst are reset to zero by a reset of the nse-8g using the rstb input. pmctst is reset when csb is high; pmcatst is reset when csb is high and rstb is low. pmctst and pmcatst can also be reset by writing a logic 0 to the corresponding register bit. access to this register is not affected by the test mode address force functions in registers 1001h and 1002h. hizio, hizdata the hizio and hizdata bits control the tri-state modes of the nse-8g . while the hizio bit is a logic one, all output pins of the nse-8g except the data bus and output tdo are held tri-state. the microprocessor interface is still active. while the hizdata bit is a logic one, the data bus is also held in a high-impedance state which inhibits microprocessor read cycles. the hizdata bit is overridden by the dbctrl bit. iotst the iotst bit is used to allow normal microprocessor access to the test registers and control the test mode in each tsb block in the nse-8g for board level testing. when iotst is a logic one, all blocks are held in test mode and the microprocessor may write to a block?s test mode 0 registers to manipulate the outputs of the block and consequently the device outputs (refer to the ?test mode 0 details? in the ?test features? section). dbctrl the dbctrl bit is used to pass control of the data bus drivers to the csb pin. when the dbctrl bit is set to logic one and pmctst is set to logic one, the csb pin controls the output enable for the data bus. while the dbctrl bit is set, holding the csb pin low causes the nse-8g to drive the data bus and holding the csb pin high tri-states the data bus. the dbctrl bit overrides the hizdata bit. the dbctrl bit is used to measure the drive capability of the data bus driver pads.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 127 document id: pmc-2010850, issue 1 pmctst the pmctst bit is used to configure the nse-8g for pmc's manufacturing tests. when pmctst is set to logic one, the nse-8g microprocessor port becomes the test access port used to run the pmc "canned" manufacturing test vectors. as well, the analog blocks are placed in iddq mode = the digital circuitry within the analog blocks is held static the pmctst can be cleared by setting csb to logic one or by writing logic zero to the bit. pmcatst the pmcatst bit is used to configure the analog portion of the nse-8g for pmc's manufacturing tests. the pmcatst bit can be cleared by setting both csb to logic one and rstb to logic zero. pmcatst can also be cleared by writing logic zero to the bit. 11.2 jtag test port the nse jtag test access port (tap) allows access to the tap controller and the four tap registers: instruction, bypass, device identification and boundary scan. using the tap, device input logic levels can be read, device outputs can be forced, the device can be identified and the device scan path can be bypassed. for more details on the jtag port, please refer to the operations section. table 12 instruction register (length - 3 bits) instructions selected register instruction codes, ir[2:0] extest boundary scan 000 idcode identification 001 sample boundary scan 010 bypass bypass 011 bypass bypass 100 stctest boundary scan 101 bypass bypass 110 bypass bypass 111 table 13 identification register length 32 bits version number 0h part number ? nse-20g 8620h part number ? nse?8g 8621h manufacturer's identification code 0cdh device identification ? nse-20g 086200cdh device identification ? nse-8g 086210cdh
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 128 document id: pmc-2010850, issue 1 table 14 boundary scan register pin/ enable register bit cell type i.d. bit oeb_intb 121 out_cell 0 intb 120 out_cell 0 ale 119 in_cell 0 csb 118 in_cell 0 wrb 117 in_cell 1 rdb 116 in_cell 0 a[11] 115 in_cell 0 a[10] 114 in_cell 0 a[9] 113 in_cell 0 a[8] 112 in_cell 1 a[7] 111 in_cell 1 a[6] 110 in_cell 0 a[5] 109 in_cell 0 a[4] 108 in_cell 0 a[3] 107 in_cell 1 a[2] 106 in_cell 0 a[1] 105 in_cell 0 a[0] 104 in_cell 0 oeb_d[31] 103 out_cell 0 d[31] 102 io_cell 0 oeb_d[30] 101 out_cell 0 d[30] 100 io_cell 0 oeb_d[29] 99 out_cell 0 d[29] 98 io_cell 0 oeb_d[28] 97 out_cell 1 d[28] 96 io_cell 1 oeb_d[27] 95 out_cell 0 d[27] 94 io_cell 0 oeb_d[26] 93 out_cell 1 d[26] 92 io_cell 1 oeb_d[25] 91 out_cell 0 d[25] 90 io_cell 1 oeb_d[24] 89 out_cell - d[24] 88 io_cell - oeb_d[23] 87 out_cell - d[23] 86 io_cell - oeb_d[22] 85 out_cell - d[22] 84 io_cell -
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 129 document id: pmc-2010850, issue 1 pin/ enable register bit cell type i.d. bit oeb_d[21] 83 out_cell - d[21] 82 io_cell - oeb_d[20] 81 out_cell - d[20] 80 io_cell - oeb_d[19] 79 out_cell - d[19] 78 io_cell - oeb_d[18] 77 out_cell - d[18] 76 io_cell - oeb_d[17] 75 out_cell - d[17] 74 io_cell - oeb_d[16] 73 out_cell - d[16] 72 io_cell - oeb_d[15] 71 out_cell - d[15] 70 io_cell - oeb_d[14] 69 out_cell - d[14] 68 io_cell - oeb_d[13] 67 out_cell - d[13] 66 io_cell - oeb_d[12] 65 out_cell - d[12] 64 io_cell - oeb_d[11] 63 out_cell - d[11] 62 io_cell - oeb_d[10] 61 out_cell - d[10] 60 io_cell - oeb_d[9] 59 out_cell - d[9] 58 io_cell - oeb_d[8] 57 out_cell - d[8] 56 io_cell - oeb_d[7] 55 out_cell - d[7] 54 io_cell - oeb_d[6] 53 out_cell - d[6] 52 io_cell - oeb_d[5] 51 out_cell - d[5] 50 io_cell - oeb_d[4] 49 out_cell - d[4] 48 io_cell - oeb_d[3] 47 out_cell - d[3] 46 io_cell - oeb_d[2] 45 out_cell - d[2] 44 io_cell -
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 130 document id: pmc-2010850, issue 1 pin/ enable register bit cell type i.d. bit oeb_d[1] 43 out_cell - d[1] 42 io_cell - oeb_d[0] 41 out_cell - d[0] 40 io_cell - logic one 39 in_cell - logic one 38 in_cell - logic one 37 in_cell - logic one 36 in_cell - logic one 35 in_cell - logic one 34 in_cell - logic one 33 in_cell - logic one 32 in_cell - logic one 31 in_cell - logic one 30 in_cell - logic one 29 in_cell - logic one 28 in_cell - logic one 27 in_cell - logic one 26 in_cell - cmp 25 in_cell - sysclk 24 in_cell - rc1fp 23 in_cell - oeb_tc1fp 22 out_cell - tc1fp 21 out_cell - rstb 20 in_cell - logic one 19 in_cell - logic one 18 in_cell - logic one 17 in_cell - logic one 16 in_cell - logic one 15 in_cell - logic one 14 in_cell - logic one 13 in_cell - logic one 12 in_cell - logic one 11 in_cell - logic one 10 in_cell - logic one 9 in_cell - logic one 8 in_cell - logic one 7 in_cell - logic one 6 in_cell - logic one 5 in_cell - logic one 4 in_cell -
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 131 document id: pmc-2010850, issue 1 pin/ enable register bit cell type i.d. bit logic one 3 in_cell - logic one 2 in_cell - logic one 1 in_cell - logic one 0 in_cell - notes 1. when set high, intb will be set to high impedance. 2. enable cell oeb_ pinname , tristates pin pinname when set high. 3. oeb_intb is the first bit of the boundary scan chain. 4. cells ?logic one? are input observation cells whose input pad is bonded to vdd internally. 11.2.1 boundary scan cells in the following diagrams, clock-dr is equal to tck when the current controller state is shift-dr or capture-dr, and unchanging otherwise. the multiplexer in the center of the diagram selects one of four inputs, depending on the status of select lines g1 and g2. the id code bit is as listed in the boundary scan register, table 14. figure 13 input observation cell (in_cell) input pad d c clock-dr scan chain out input to internal logic shift-dr scan chain in 1 2 mux 1 2 1 2 1 2 i.d. code bit idcode g1 g2
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 132 document id: pmc-2010850, issue 1 figure 14 output cell (out_cell) extest d c d c g1 g2 12 mux g1 1 1 mux output or enable from system logic scan chain in scan chain out output or enable shift-dr clock-dr update-dr 12 12 12 idoode i.d. code bit figure 15 bidirectional cell (io_cell) d c d c g1 1 1 mux output from internal logic scan chain in scan chain out extest output to pin shift-dr clock-dr update-dr input from pin input to internal logic g1 1 2 mux 1 2 1 2 1 2 g2 idcode i.d. code bit
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 133 document id: pmc-2010850, issue 1 figure 16 layout of output enable and bidirectional cells output enable from internal logic (0 = drive) input to internal logic output from internal logic scan chain in scan chain out i/o pad out_cell io_cell
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 134 document id: pmc-2010850, issue 1 12 operation there are several important aspects regarding the operation of nse-based switch fabrics; these are dealt with in turn in the following sections. 12.1 software default settings 12.1.1 setting the t8te time-slot configuration #1 register set the first t8te time-slot configuration register to 0000aaaah. this sets t8te to lpt mode so that low order path signals are encoded in outgoing 8b/10b characters. or, set to 00005555h to set t8te to hpt mode to ensure v1/v2 bytes are preserved. 12.1.2 setting the t8te time-slot configuration #2 register set the second t8te time-slot configuration register to 000000aah. this sets t8te to lpt mode so that low order path signals are encoded in outgoing 8b/10b characters. or, set to 00000055h to set t8te to hpt mode to ensure v1/v2 bytes are preserved. 12.1.3 configuring the nse-8g to use fewer links the nse-8g powers up with the software digital reset disabled, software analog reset disabled and individual link reset enabled. this means that only the digital blocks are enabled post hardware reset (since setting channel reset also disable the associated analog blocks). the csu by default will be start upon nse-8g powers up; it can only be reset by the firmware writing logic one to the areset bit in nse-8g master reset register (000h). by writing logic zero to appropriate channels in nse-8g individual channel reset register (001h) will bring the associated link out of reset and operational for normal mode operation. when fewer than 32/12 links are used in the nse-8g 20g/8g, the unused links should be disabled individually by writing logic one to the appropriate nse-8g individual channel reset register (001h) bit. writing logic one to bit n of nse-8g individual channel reset register will disable the r8td, ilc, and t8te of channel n. this reset controls both the digital as well as the analog reset inputs of the r8td and t8te. the analog reset input of r8td and t8te gates the analog reset and enable output that is used to disable the associated dru/rxlv, piso/txlv analog blocks. this will cause the entire link from input n to output n to be disabled. reset states of various operation modes post hardware reset: register 000h : dreset ?0? register 000h : areset ?0? register 001h : reset ?0xffffffff?
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 135 document id: pmc-2010850, issue 1 digital test mode: register 000h : dreset ?0? register 000h : areset ?0? register 001h : reset ?0x00000000? analog test mode: register 000h : dreset ?0? register 000h : areset ?1? register 001h : reset ?0xffffffff? holding pmcatstb will overide channel resets to analog blocks during analog tests. software analog reset areset will override pmcatstb to reset analog blocks even when pmcatstb is active. releasing pmcatstb will return all analog blocks to software control. normal mode: register 000h : dreset ?0? register 000h : areset ?0? register 001h : reset link dependent figure 17 shutting down a link r8td t8te dcb ilc ilc piso txlv rxlv dru reset[n] from register 001h
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 136 document id: pmc-2010850, issue 1 12.1.4 pcb design notes to maintain flexibility, all unused lvds inputs and outputs should be left floating. this will prevent accidental damage caused by firmware enabling outputs, or releasing resets of inactive ports. 12.2 ?c1? synchronization any nse/sbs fabric can be viewed as a collection of five ?columns? of devices: column 0 consists of the ingress flow from the load devices (e.g., some sbi device); column 1 consists of the ingress flow through the sbs devices; column 2 consists of the nse-8g device; column 3 consists of the egress flow through the sbs devices; and column 4 consists of the egress flow through the load devices (e.g. some sbi device). note that the devices in columns 0 and 4 are sbi bus devices while columns 1 and 3 are sbs or sbs-lite devices. the dual column references refer to their two separate simplex flows. path-aligned sts-12 frames are pipelined through this structure in a regular fashion, under control of a single clock source and frame pulse. there are latencies between these columns, and these latencies may vary from path to path. the following design is used to accommodate these latencies. a timing pulse for sbi frames (2khz, 500 = s) is generated and fed to each device in the fabric. each chip has a framedelay register (rc1dly) which contains the count of 77.76 mhz clock ticks that device should delay from the reference timing pulse before expecting the c1 characters of the ingress sts-12 frames to have arrived. the base timing pulse is called t . the delays from t based on the settings of the rc1dly registers in the successive columns of the devices are called t 0 , ? t 4 . the first signal, t 1 (equal to t 0 ), determines the start of an sts-12 frame; this signal is used to instruct the ingress load devices (column 0) to start emitting an sts-12 frame (with its special ?c1? control character) at that time. t i is determined by the customer, based on device and wiring delays to be approximately the earliest time that all ?c1? characters will have arrived in the ingress fifos of the t i column of devices. t i is selected to provide assurance that all ?c1? characters have arrived at the i th column. the i th column of devices use the t i signal to synchronize emission of the sts-12 frames. the ingress fifos permit a variable latency in c1 arrival of up to 16 clock cycles. note: the sbs device, being a memory switch adds a latency of one complete frame or row plus a few clock ticks to the data.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 137 document id: pmc-2010850, issue 1 figure 18 ?c1? synchronization control ingress sbi device ingress sbs (1 frame delay) egress sbs (1 frame delay) 500 s source delay t 1 t 0 , t 1 t 2 t 3 t 4 delay 125 s t at 0 s egress sbi device delay t 2 delay t 3 delay t 4 t 0 nse delay 125 s (no delay t delay through ingress sbi device) 12.3 synchronized control setting changes the nse-8g and sbs support dual switch control settings. these dual settings permit one bank of settings to be operational while the other bank is updated as a result of some new connection requests. the cmp input selects the current operational switch control settings. cmp is sampled by the nse-8g on the rc1fp . the internal blocks sample the registered cmp value as they receive the next c1 character after a delay of rc1dly. the new cmp value is applied on the first a1 character of the following sts-12 frame. this switchover is hitless; the control change does not disrupt the user data flow in any way. this feature is required for the addition of arbitrary new connections, as existing connections may need to be rerouted (see the discussion of the connection routing algorithm in this document). the ds0-granularity switch settings ram in organized into two control settings banks, these are switched by the above mechanisms on c1 boundaries. the nse-8g also has to coordinate the switching of the connected sbs devices (if using the in-band link facility), so a broader understanding of the issues is required. the following sections provide examples. 12.3.1 sbs/nse-8g systems with ds0 and cas switching when building a ds0 and channel associated signaling switching system with the sbs, sbs-lite and nse-8g devices the overall timing is based on the cas signaling multiframe on the sbi bus. in this configuration the delay through the sbs devices is a single 125 s sbi frame plus a few 77.76 mhz clocks and the delay through the nse-8g is a few 77.76 mhz clocks. a single c1fp frame synchronization signal is distributed around the system. internal to the sbs and nse-8g devices are programmable offsets used to account for propagation delays through the system. the key constraint is that all sbi frames are aligned going into the nse-8g device. compatible devices are temux-84, freedm-336, freedm-336-84 bond-out, s/uni-ima- 84, and other future sbi336 devices.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 138 document id: pmc-2010850, issue 1 the sbs and nse-8g devices have two configuration pages controlling the switching of each ds0 with cas. the sbs has independent configuration pages for each direction of data flow through the device. the nse-8g has one set of configuration pages. system configuration changes are made by writing to the offline configuration page in all affected devices and then swapping from the old configuration page to the new configuration page. the tcmp and ocmp signals control the current configuration page of the sbs and the cmp signal controls the current configuration page of the nse. swapping of configuration pages must be aligned to frame switching through the system to avoid any possible data corruption. the tcmp, ocmp and cmp signals are sampled with the sbs ic1fp and rc1fp signals and the nse-8g rc1fp signals respectively. the cmp signals can be connected together at the expense of having to ensure all device configuration pages are current. figure 19 shows how the devices are connected together. the following timing diagrams show the external signals and the internal device frame alignment signal generated from the programmed delays. although the cmp signals are sampled externally with the c1fp signals they are also delayed internally to coincide with the internally delayed frame signals. these are also shown in the timing diagram. all internal signals are identified by the .int suffix. figure 19 temux-84?/sbs/nse/sbs/aal1gator-32? system ds0 switching with cas sbi336 sbi336s sbi336s sbi ic1fp tcmp sbs #1 oc1fp rc1fp ocmp dc1fp temux84 ac1fp dc1fp aaligator32 ac1fp rc1fp cmp nse rc1fp ocmp oc1fp sbs #2 ic1fp tcmp sbs#2 ocmp nse cmp sbs #1 tcmp c1fp sbs#2 tcmp sbs #1 ocmp
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 139 document id: pmc-2010850, issue 1 figure 20 cas multiframe timing t1 signaling mf #1 t1 signaling mf #2 e1 signaling mf #1 e1 signaling mf #2 e1 signaling mf #3 e1 0us 2500us 5000us c1fp all c mps frame alignment sbi fram e tim e t1 multiframe e1 multiframe figure 21 switch timing dsos with cas 0us 250us c1fp all c mps sbi frame time internal sigs sbs#1 ic1fp.int nse rc1fp.int sbs#2 rc1fp.int sbs#2 oc1fp.int sbs#1 tcmp.int nse cmp.int sbs#2 ocmp.int 12.3.2 sbs/nse-8g systems switching ds0s without cas this is very similar to the ds0 switching system configuration with cas described in the previous section. the only difference is that in this system the global c1fp can be reduced to every sbi multiframe rather than the longer 48-frame sbi bus signaling multiframe. the advantage is that there is less latency when making switch configuration changes via the cmp signals.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 140 document id: pmc-2010850, issue 1 the following diagram shows the system with the freedm-336?, which does not require channel associated signaling. notice that the data latency through the system is the same as the case when switching ds0s with cas. figure 22 temux-84/sbs/nse/sbs/freedm-336 system ds0 switch no cas sbi336 sbi336s sbi336s sbi336 ic1fp tcmp sbs #1 oc1fp rc1fp ocmp dc1fp temux84 ac1fp dc1fp freedm336 ac1fp rc1fp cmp nse rc1fp ocmp oc1fp sbs #2 ic1fp tcmp sbs#2 ocmp nse cmp sbs #1 tcmp c1fp sbs#2 tcmp sbs #1 ocmp the following timing diagram shows the system timing when in this configuration.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 141 document id: pmc-2010850, issue 1 figure 23 switch timing - dsos without cas 0us 250us 500us c1fp all c mps sbi frame time internal sigs sbs ic1fp.int nse rc1fp.int sbs rc1fp.int sbs oc1fp.int sbs tcmp.int nse cmp.int sbs ocmp.int 12.3.3 sbs/nse-8g non-ds0 level switching with sbi336 devices the sbs and nse-8g supports another mode of operation that has lower latency and lower power when not switching at the ds0 level. in this mode both of these devices become a column switch rather than a ds0 switch. this also saves sw configuration since only one row of the switch configuration rams has to be configured rather than all nine rows. when switching ds0 through the system the sbs must store an entire frame of ds0s before routing them to the destination to allow for the last ds0 of a frame to be switched to the first ds0 of the output. when doing column switching only one row of the sbi structure needs to be stored before switching can take place. figure 22 from the previous section can be used here. the following timing diagram shows the system timing for this mode of operation.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 142 document id: pmc-2010850, issue 1 figure 24 non ds0 switch timing 0us 250us 500us c1fp sbs#1 tcmp nse cmp sbs#2 ocmp sbi frame time internal sigs sbs ic1fp.int nse rc1fp.int sbs rc1fp.int sbs oc1fp.int sbs#1 tcmp.int nse cmp.int sbs#2 ocmp.int 12.4 nse-8g cpu interaction with the switching cycle when using the ilc an interrupt is made available to the nse-8g cpu called the frame interrupt this occurs at the start of the internal frame and marks a time in the nse-8g where updates to the system page bits can occur. this interrupt is maskable and would normally be masked. the cpu will need to enable this interrupt before a page switch is required, then respond to this interrupt immediately and complete writing the new page bit settings (a two double word operation) within 27 s. this is required as the ilc will sample the sbs page bits (in the ilcs) once during the frame before the first message is assembled and sent (starting at the beginning of row 3). if the page bits are updated late, the sbs pages will switch a frame late, which means the nse-8g dcb may switch early giving disastrous results. the nse-8g cpu will have the rest of the frame to signal a page switch to the dcb as this is sampled on the next frame
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 143 document id: pmc-2010850, issue 1 1 234 1 234 rc1fp (ext) nse c1fp (int) nse frame interrupt enable frame interrupt write new sbs page words write new dcb page bit and disable frame interrupt nse cpu tasks sbs sample new bit sbs samples new page bits and set up page switch switch occurs in the sbs dcb sample new bit switch occurs in the nse nse dcb samples cmp bit and set up page switch outgoing messages outgoing messages 12.5 controlling frame alignment in the receive port after external data corruption on any port it may be necessary to force oca to reset the alignment of the r8td block. in order to detect this out of alignment condition, three hardware functions are implemented for each port. the registers are: ? ?correct r8td_rx_c1 pulse monitor?, 012h ? ?unexpected r8td_rx_c1 pulse interrupt?, 013h ? ?missing r8td_rx_c1 pulse interrupt?, 014h these are qualified against a delayed version of the rc1fp input, which should occur every 4 or 48 frames and in agreement with mf_swap mode (dcb configuration register, 04ch). if all active ports are using carrying the same frequency of c1 frame pulses (1 in 4 or 1 in 48) then the unexpected interrupt (013h) should be used to signal that a c1 code word was detected at the wrong time, software can then poll the monitor register (012h) to see if the error condition is permanent.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 144 document id: pmc-2010850, issue 1 if some links are switching ds0 traffic (?1 in 48? frame mode) and some are not (?1 in 4? frame mode), the input rc1fp and the qualifying signal from the dcb (from mf_swap), will be running at ?1 in 48? frame mode. the links in ?1 in 48? frame mode should use the unexpected interrupt while the others should use the missing interrupt. if a link no longer has any c1 activity, the firmware should assume the link has lost alignment, and should force r8td oca for the port. these instructions assume the pmc nse-8g device driver is not being used. if the supplied driver is being used, this will all be handled within that driver. 12.6 ds0 cross-bar switch (dcb) operation while the dcb is the space switch central to the nse-8g it also contains the dcb c1 delay register. this register must be programmed with the delay (in 77.76 mhz clock cycles) between rc1fp (rc1dly) and the expected arrival time in the r8td sipo of the c1 character. this value is expected to be in the order of 51 clock cycles + 9720 or +1080 for sbi mode or telecombus mode respectively. the 51 value is approximate and very dependant on the system architecture and transmission line lengths between the sbs and nse-8g components. this must be obtained empirically by the system designer during product commissioning. figure 25 architecture of the ram input interface c d 160 160 offcfg[159:0] b 160 160 5 160 160 5 oncfg[159:0] refclk portcfg[4:0] portaddr[4:0] wordcfg[159:0] 30 f . . . e 30 pgndin[159:0] accmde updatev cfgo[29:0] 12.6.1 configuring the dcb using port transfer mode in port transfer mode, the microprocessor updates only one configuration entry within a word of offline connection memory page. the steps to perform a port transfer are shown in the following example:
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 145 document id: pmc-2010850, issue 1 example: suppose one wishes to change the cross bar to map din[10][12:0] to dout[6][12:0] for just the 4097th byte of the frame and wishes to keep all other mappings of the 4097th byte the same. steps: 1. cpu writes 0x8a061000 to the dcb access mode register (i.e., wrb=1, accmde=0, portcfg[4:0]=0x0a, portaddr[4:0]=0x06, wordaddr[13:0]=0x1000). causes mux b to switch in portcfg at port 6. causes mux c to switch in mux b. triggers a read from offline memory connection page at location 0x1000. 2. wait four sysclk cycles. 3. writes 0x0a061000 to the dcb access mode register (i.e., wrb=0, accmde=0, portcfg[4:0]=0x0a, portaddr[4:0]=0x06, wordaddr[13:0]=0x1000). causes mux b to switch in portcfg at port 6. causes mux c to switch in mux b. triggers a write from register d to offline connection memory page at location 0x1000. 4. wait four sysclk cycles before returning to step 1 to perform another mapping change. 12.6.2 configuring the dcb using word transfer mode: in word transfer mode, the microprocessor updates the entire word of offline connection memory page. the steps to perform a word transfer is shown in the following example: example: suppose one wishes to change the entire cross bar mapping from din to dout for just the 4097th byte of the frame. steps: 1. cpu writes new mapping to the configuration 31-30 port register. 2. cpu writes new mapping to the configuration 29-24 port register. 3. cpu writes new mapping to the configuration 23-18 port register. 4. cpu writes new mapping to the configuration 17-12 port register. 5. cpu writes new mapping to the configuration 11-6 port register. 6. cpu writes new mapping to the configuration 5-0 port register . 7. cpu write 0x40001000 to the dcb access mode register. causes mux c to switch in wordcfg.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 146 document id: pmc-2010850, issue 1 triggers a write to offline connection memory page at 0x1000. go to step 1 to begin the mapping change for a new byte in the frame. 12.6.3 reading configurations it is possible to read configurations from the offline connection memory page. the following example shows this reading operation. example: suppose one wishes to read which din ports map to dout[17:12][12:0] for the 4097th byte of the frame within the offline connection memory page. steps: 1. cpu writes 0x80081000 to the dcb access mode register. (a binary value of 010xx on portaddr[4:0] indicates to supply the mapping the configuration port 17-12 register.) 2. wait for six sysclk cycles. 3. cpu reads the mapping from the dcb configuration output register. note: 1. the access mode register should not be accessed more frequently than once ever 4 sysclk cycles when initiating write transfers. 2. when initiating a read from the offline connection memory page to the configuration output register, there is a latency of 6 sysclk cycles from when a read is initiated till when valid data appears on cfg_o. 3. user should perform this operation only when there is no page swap pending (swapv = ?0?) and page copy is inactive (updatev = ?0?). 12.6.4 dcb online to offline memory page copy there are two ways in which a connection memory page copy can occur; forced and automatic. in forced mode, the cpu initiates a page copy by writing to the dcb interrupt status register. the page copy begins immediately after being initiated. in automatic mode, the auto field must be set to logic one. when a connection memory page swap occurs, the online connection memory page is copied to the offline connection memory page. interrupt generation to signal the page copying status can be enabled to simplify software scheduling by setting the updatee field in the dcb configuration register to logic one. in this mode, the updatei field in the dcb interrupt status register can be used as the interrupt signal to control the microprocessor. alternatively, the microprocessor can poll the updatev field within the dcb configuration register to detect the status of the connection memory page update logic. logic one indicates copying in progress and logic zero indicates copying complete.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 147 document id: pmc-2010850, issue 1 warning: attempting a page copy while a page swap is pending can lead to corruption of both online and offline memory pages if the page swap occurred while the page copy is in progress. 12.7 telecombus mode operation in telecombus mode operation, only 1080 words of the configuration ram are utilized. this same configuration is repeated nine times for switching the entire 9720 byte oc-12 frame. in this mode, rc1fp is flywheeled internally every frame so that page swaps can also occur at this frequency. the oc1fp output pulse that is used to resynchronize external tsbs occurs at every 4 th frame. to configure this mode of operation, use the following programming steps. note, the order in which these steps are followed is irrelevant. 1. program the dcb frame size register (0x4a) to 1079. this programs the dcb to use just 1080 location of the rams. 2. program the dcb mf_swap bits in configuration register (0x4c) to 00. this will program the dcb to effect page changes at every 9720 byte frame when a page swap request is received. oc1fp will be output at every 4 th frame. cmp inputs will be sampled every frame at the internally flywheeled rc1fp location. if enabled, framei will occur every frame at the internally flywheeled rc1fp location. 12.8 sbi column mode operation in sbi column mode operation, only 1080 rows of the configuration ram is utilized, this same configuration is repeated nine times for switching the entire 9720 byte oc12 frame and 36 times to form the 4-frame multiframe. in this mode, rc1fp is flywheeled internally every fourth frame so that page swap can also occur at this frequency. oc1fp output that is used to resynchronize external tsbs also occurs at every fourth frame. to configure this mode of operation, use the following programming steps. note, the order in which these steps are followed is irrelevant. 1. program the dcb frame size register (0x04a) to 1079. this programs the dcb to use just 1080 location of the rams. 2. program the mf_swap bits in dcb configuration register (0x04c) to 01. this will program the dcb to effect page changes at every 4 x 9720 frame when a page swap request is received. oc1fp will be output at every 4 frame. cmp inputs will be sampled every 4 frame at the internally flywheeled rc1fp location.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 148 document id: pmc-2010850, issue 1 if enabled, framei will occur every 4 frame at the internally flywheeled rc1fp location. 12.9 sbi ds0 mode operation in sbi ds0 mode operation, all 9720 words of the configuration ram are utilized. this same configuration is repeated four times to switch the 4-frame multiframe. in this mode, rc1fp is flywheeled internally every four frames so that page swaps can also occur at this frequency. a pulse on the oc1fp output that is used to resynchronize external tsbs also occurs every four frames. to configure this mode of operation, use the following programming steps. note, the order in which these steps are followed is irrelevant. 1. program the dcb frame size register (0x4a) to 9719. this programs the dcb to use all 9720 location of the rams. 2. program the mf_swap bits in dcb configuration register (0x4c) to 10. this will program the dcb to effect page changes at every 4 x 9720 frame when a page swap request is received. oc1fp will pulse high at every 4th frame. cmp inputs will be sampled every 4th frame at the internally flywheeled rc1fp location. if enabled, framei will occur every 4th frame at the internally flywheeled rc1fp location. 12.10 sbi ds0 with cas mode operation in sbi ds0 with cas mode operation, all 9720 words of the configuration ram are utilized. this same configuration is repeated 48 times to switch the 48 frame multiframe. in this mode, rc1fp is flywheeled internally every 48th frame so that page swaps can also occur at this frequency. a pulse on the oc1fp output that is used to resynchronize external tsbs also occurs at every 48th frame. to configure this mode of operation, use the following programming steps. note, the order in which these steps are followed is irrelevant. 1. program the dcb frame size register (0x4a) to 9719. this programs the dcb to use all 9720 location of the rams. 2. program the mf_swap bits in dcb configuration register (0x4c) to 11. this will program the dcb to effect page changes at every 48 x 9720 frame when a page swap request is received. oc1fp will pulse every 48th frame.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 149 document id: pmc-2010850, issue 1 cmp inputs will be sampled every 48th frame at the internally flywheeled rc1fp location. if enabled, framei will occur every 48 frame at the internally flywheeled rc1fp location. note: it is vital to ensure that switching of the ds0 bytes containing cas bits be performed correctly through software configuration. that is, these bytes should all be preserved and switched to the same output link to preserve the cas for downstream devices. 12.11 ilc operation operating each of the 32 ilc blocks requires the same procedure. each ilc will be operating independently and wait states required for each ilc can be satisfied by interleaving the access cycles of several ilc blocks together. the ilc is synchronized by the c1 pulse accompanying the input data stream on the telecombus. it preloads a 9720 counter using this c1 pulse. c1 as shown in figure 26, will be high when the byte in column 25, row 1 is on the input data pins. a 2 bit counter is also kept to keep track of the 4-frame multiframe, ie. 4 x 9720 count. this is indicated by c1 being present only in the first frame of a multiframe. (could be 1in 4 or higher multiples). figure 26 c1 position in the first row a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 123456789101112131415161718192021222324 c1 25 row 1 column the ilc inserts and retrieves messages from the transport overhead of the sonet/sdh frame on the telecom-bus. figure 27 illustrates the four rows carrying the four messages per frame. the messages are inserted on an availability basis into the four message rows shown in figure 27, rows 3,6,7 and 8. the header is always placed into columns 1 and 2. the message itself is always placed msbyte first into columns 3 ? 34, in fifo order. the crc-16, calculated over the header and message, is placed into columns 35 and 36. if no message is available, internal hardware will automatically insert zeros into the message bytes. even if no message is available (32 of 36 bytes), the header(2 of 36 bytes) can still be carrying valid bits for the far end, as such even if the message is invalid, the header and crc are still generated and inserted. the header?s valid bit is not set as an indication to the far end to discard the message (not insert the null message into its rxfifo). 12.12 ilc cpu operations 12.12.1 accessing the transmit message fifo access registers in the following order:
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 150 document id: pmc-2010850, issue 1 1. write 00000001h to the ilc transmit misc. status and fifo synch register to initiate a new message write sequence (tx_xfer_sync). 2. loop through the next two operations until the message is transferred. 3. write the transmit fifo data register. 4. wait for the tx_fi_busy bit to be logic zero (read ilc transmit misc. status and fifo synch register) or wait for three sysclk cycles and then continue. this wait time can be used to access other registers, just as long as the transmit fifo data register is not changed during this time. notes on using the tx_xfer_sync if all messages transmitted are eight dwords in length, then writing the tx_xfer_sync bit is optional. when transmitting a message immediately following a short message, writing the tx_xfer_sync bit is mandatory. when transmitting messages longer than eight dwords, writing the tx_xfer_sync bit every eight dwords is optional. 12.12.2 accessing the receive message fifo access the registers in the following order: this procedure is outline only. full operation is shown in the code snippet below. 1. write 00000001h to the receive auxiliary, status and fifo synch register to initiate a new message read sequence. 2. loop through the next two operations until message is transferred. 3. read the receive fifo data register. 4. wait for the busy bit to equal ?0? (read receive status register ah) or wait for three sysclk cycles and then continue. this wait time can be utilized accessing other registers, just as long as the receive fifo data register is not read again during this time. the following psuedo code shows the recommended procedure for accessing the receive message fifo. procedure message_receive is variable dword_rd_cnt : natural := 0; variable msg_done : boolean := false; variable polled_rx_mode : boolean := false; variable msg_lvl_loop : natural := 0; variable msgs_rd : natural := 0; begin --
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 151 document id: pmc-2010850, issue 1 -- get the msg_lvl -- rd(rx_stts); while rx_stts_valid = '0' loop rd(rx_stts); end loop; msg_lvl_loop := rx_msg_lvl; -- -- now check the rx_sync_done status to be sure we're not going to skip -- the 1st message... -- if rx_sync_done = '0' then -- -- do the rx_xfer_sync -- wr(rx_stts, "00000000000000000000000000000001"); -- -- poll the rx_fi_busy bit -- rd(rx_stts); while rx_fi_busy = '1' loop rd(rx_stts); end loop; end if; -- -- next rx msg buffer is now synched and we know how many messages we have. -- just read the messages out. -- msgs_rd := 0; tst_report("processin g " & to_str(msg_lvl_loop ) & " messages."); while msgs_rd < msg_lvl_loop loop -- loop on read value of rx_msg_lvl -- -- check the crc_err bit for this message -- rd(rx_stts); rxmsg.crc_err := crc_err_reg; --- simulation stuff -- -- this code skips errored messages. -- while crc_err_reg = '1' and rndm_skip_msg_mode loop tst_report("errored message received and being skipped..."); if rx_sync_done = '1' then wr(rx_stts, "00000000000000000000000000000001"); else -- -- we're in this loop 2nd time without a good msg inbetween. need 2 -- rx_xfer_sync writes to do a message skip -- wr(rx_stts, "00000000000000000000000000000001"); -- -- poll the bit here before starting next message. -- rd(rx_stts); while rx_fi_busy = '1' loop rd(rx_stts); end if; rx_msg_cnt_o <= rx_msg_cnt_o + 1; msgs_rd := msgs_rd + 1; --
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 152 document id: pmc-2010850, issue 1 -- poll the bit here before startiong next message. -- rd(rx_stts); while rx_fi_busy = '1' loop rd(rx_stts); end loop; -- -- check the crc_err bit for the next message -- rd(rx_stts); rxmsg.crc_err := crc_err_reg; end loop; -- -- now we should have a good message or an errored message we want to read -- note: we might have skipped the last message in the code above. -- read the message if we have any. -- if msgs_rd < msg_lvl_loop then msg_done := false; dword_rd_cnt := 0; rxmsg.payload := (others => 0); while dword_rd_cn t < 8 and not msg_done loop rd(rx_dat); -- the returned data is part of the payload --- simulation stuff. should replace with s/w stuff for j in 3 downto 0 loop rxmsg.payload((dword_rd_cnt*4)+(3-j)) := conv_integer(reg_rd_data(8*j+7 downto 8*j)); end loop; if dword_rd_cn t = 0 then rndm_rx_payload_len <= conv_integer(reg_rd_data(31 downto 24)); end if; --- end simulation stuff. dword_rd_cnt := dword_rd_cnt + 1; if polled_rx_mode then rd(rx_stts); while rx_fi_busy = '1' loop rd(rx_stts); end loop; else -- -- fixed delay to allow to ensure 4 sysclks plus o/p delay between rdb edges -- wait for 36 ns; end if; -- -- optional s/w algorithm to determine if the msg is done before 8 dwords -- have been read. in this case for simulation the test the msg_done is set -- when we've read the number of dwords as indicated in the 1st message -- payload byte. -- if dword_rd_cnt = rndm_rx_payload_len then msg_done := true; end if; if msg_done and dword_rd_cn t < 8 then -- -- we're on a short message. need to do rx_xfer_sync --
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 153 document id: pmc-2010850, issue 1 tst_report("executing receive buffer resyn c"&" following short message of length " & to_str(dword_rd_cnt) & "."); wr(rx_stts, "00000000000000000000000000000001"); -- -- poll the bit here before startiong next message. -- rd(rx_stts); while rx_fi_busy = '1' loop rd(rx_stts); end loop; end if; end loop; --- simulation stuff check_rx_msg(payload_chk,no_header_chk); -- check payload only. rx_msg_cnt_o <= rx_msg_cnt_o + 1; --- end simulation stuff msgs_rd := msgs_rd + 1; else -- msgs_rd = msg_lvl_loop -- -- when we think we're done check that we really are. -- update the current value of rx_msg_lvl. allows for the case where a -- message has arrived while processing. -- at this point we have read all the messages we thought we had at the -- start of the loop so whatever number is returned now is the number of -- new messages receieved while we've been reading messages. -- unless we're running real slow this should only be 1 or 0. -- we adjust our loop variable by this amount to keep the loop going -- long enough to get the extra messages received. -- rd(rx_stts); while rx_stts_valid = '0' or rx_fi_busy = '1' loop rd(rx_stts); end loop; if rx_msg_lv l > 0 then tst_report("message(s) received while processing messages"); end if; -- -- note in this code i'm not checking for more messages received than -- read. we'd be in real trouble in the system in this case! we -- also can't get there in the sim! -- msgs_rd := msgs_rd - rx_msg_lvl; end if; end loop; end message_receive; 12.12.3 handling the transmit header page bits if the ipage bits are changed, they are not sent in the header bits until the next frame. they will be continually sent for each message in subsequent frames until they change again. user, link and aux bits when any of these bits change they are sent in the header bits of the next message. they will be continually sent for each subsequent message until they change again.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 154 document id: pmc-2010850, issue 1 12.12.4 handling the receive header 12.12.5 handling interrupts all interrupts are masked on startup, and should not be enabled until the link initializes. 12.12.6 bypass function functional block transmit and receive functions can be disabled independently (or together) by writing a ?1? to: ? the lsb (tx_bypass) of the transmit control register to enable transmit bypass. ? the lsb (rx_bypass) of the receive control register to enable receive bypass. when in bypass mode, message fifo rams are disabled and the ilc functions as a 2-stage pipeline. when tx_bypass is set, writes to the transmit fifo are ignored and when rx_bypass is set, reads from the receive fifo return random data.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 155 document id: pmc-2010850, issue 1 figure 27 transport overhead affected by ilc a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 19 20 21 22 23 24 c1 25 26 row 1 column j0/z0 (c1) j0/z0 (c1) j0/z0 (c1) j0/z0 (c1) j0/z0 (c1) j0/z0 (c1) j0/z0 (c1) j0/z0 (c1) j0/z0 (c1) j0/z0 (c1) 27 28 29 30 31 32 33 34 35 36 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 f1 row 2 d3 row 3 row 4 row 5 row 6 row 7 row 8 f1 f1 f1 f1 f1 f1 f1 f1 f1 f1 f1 d1 d2 h1 h2 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 b2 k1 k2 k2 k2 k2 k2 k2 k2 k2 k2 k2 k2 k2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 k1 k1 k1 k1 k1 k1 k1 k1 k1 k1 k1 d6 d4 d5 d9 d7 d8 d12 d10 d11 s1/z1 m0 m1/ z2 e2 undef e2 undef e2 undef e2 undef e2 undef e2 undef e2 undef e2 undef e2 undef e2 undef e2 undef e2 undef s1/z1 s1/z1 s1/z1 s1/z1 s1/z1 s1/z1 s1/z1 s1/z1 s1/z1 s1/z1 s1/z1 m0 m1/ z2 m0 m1/ z2 m0 m1/ z2 m0 m1/ z2 m0 m1/ z2 m0 m1/ z2 m0 m1/ z2 m0 m1/ z2 m0 m1/ z2 m0 m1/ z2 m0 m1/ z2 d1 d4 d7 d10 d1 d4 d7 d10 d1 d4 d7 d10 d1 d4 d7 d10 d1 d4 d7 d10 d1 d4 d7 d10 d1 d4 d7 d10 d1 d4 d7 d10 d1 d4 d7 d10 d1 d4 d7 d10 d1 d4 d7 d10 d2 d5 d8 d11 d2 d5 d8 d11 d2 d5 d8 d11 d2 d5 d8 d11 d2 d5 d8 d11 d2 d5 d8 d11 d2 d5 d8 d11 d2 d5 d8 d11 d2 d5 d8 d11 d2 d5 d8 d11 d2 d5 d8 d11 d3 d6 d9 d12 d3 d6 d9 d12 d3 d6 d9 d12 d3 d6 d9 d12 d3 d6 d9 d12 d3 d6 d9 d12 d3 d6 d9 d12 d3 d6 d9 d12 d3 d6 d9 d12 d3 d6 d9 d12 d3 d6 d9 d12 row 9 row 1 row 2 row 3 row 4 row 5 row 6 row 7 row 8 row 9 j0/z0 (c1) if a message is available, it will be inserted into the next message row available. if the page bits are changed, they are not sent in the header bits until the first message in the next frame. they will be continually sent until they change again. all other header bits are sent immediately. all ilc interrupts are masked on startup, and should not be enabled until the ilc links initialize.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 156 document id: pmc-2010850, issue 1 12.13 switch setting algorithm nse/sbs fabrics require an algorithm to map from customers? connection requirements to settings in the switch function control registers in these devices. four constraints apply to this algorithm: ? the algorithm must succeed for arbitrary permutation requests (i.e., neither the fabric nor thealgorithm can fail to connect any one-to-one connection request). ? the algorithm must permit connection of 2-cast requests (port replication for either snooping or for advanced redundancy fabrics). in fabrics with spare capacity and multicast/broadcast servers, the algorithm must permit mapping of multicast/broadcast requests, up to the capacity of the fabric and the servers. ? this algorithm must be fast enough to satisfy requirements for response to operator requests for connection changes. ? this algorithm must be fast enough to satisfy requirements for protection responses to equipment failures. there are several aspects of this problem: ? reconnection requests may be made individually in which case an incremental connection- setting algorithm is desired, or as complete batches in which case a batch algorithm may be desirable. ? reconnection requests may be pre-computed for fast protection fail-over mechanisms. 12.13.1 problem description the basic scheduling problem is to find the switch settings to properly route a set of connections. this is more formally described using the definitions in the following paragraphs. port: an sts-12 input/output data stream. the serial ports on the sbs devices and the nse- devices operate at sts-12 rates and utilize sts-12 frames. since the intention of the nse-8g is to serve as a ds0-granularity switch, these sts-12 frames must be treated as repeating on a cycle of 12*9*90 = 9720 octets. all connections considered by this algorithm are octet connections. higher aggregations of traffic are handled as collections of octets, and are ignored for the purposes of describing this algorithm. timeslot: a specific octet location in the 9720 octet cyclic structure. spacetimeslot: a timeslot on a specific port, identified by a space component and a time component: for example, octet 9 on port 3 of sbs device 2 connection: a mapping of an input spacetimeslot to an output spacetimeslot. connections come in two varieties, multicast and unicast. unicast connections are a mapping of a single input spacetimeslot to a single output spacetimeslot. multicast connections are a mapping of a single spacetimeslot to multiple output spacetimeslots. this algorithm is only concerned with the unicast problem.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 157 document id: pmc-2010850, issue 1 12.13.2 na?ve algorithm we begin by describing a simplified version of the algorithm, applied to a specific sbs/nse-8g configuration. four sbs devices are connected by one port each to an nse, which is likewise connected by one port to the egress side of each sbs device. only four ingress/egress ports on the nse-8g are in use in this application, but the ideas generalize easily to larger fabrics. information flows from left to right. each edge connects an egress port (on the left) to an ingress port (on the right); each such edge has a capacity of 9720 timeslots. for present purposes, we consider the sbss to be supporting a single p-sbi port (eight bits at 77.76 mhz, or sts-12). also, we ignore the ?standby? lvds port. this reduces the sbs from a multi-ported memory switch (which it in fact is) to a simpler two-ported (p-sbi and active s- sbi) time switch. this reduction in complexity makes the following discussion more straightforward, but does not reduce the algorithm?s ability to deal with the more complex cases introduced by the use of the four slower p-sbi ports, or by concurrent use of the standby lvds port. the nature of switching in this application is illustrated by figure 19. the two dimensional 4-x-4 matrices represent octet slots in both space (vertical) and time (horizontal). we trace through the switching processing in the following steps: matrix i represents the arrival of the 16 octets from the sbi load devices. the mapping from matrix i to matrix ii represents the time switching action of all four ingress sbss. each sbs carries out an arbitrary permutation (including 1-to-many) of the ingress time slots within each space row. the mapping from matrix ii to mat matrix rix iii represents the space switching action of the nse. during each time slot, the nse-8g carries out an arbitrary permutation (including 1-to- many) of the ingress space slots. the mapping from matrix iii to matrix iv represents the time switching action of all four egress sbss. each sbs carries out an arbitrary permutation (including 1-to-many) of the ingress time slots within each space row. it is known that any complete permutation from matrix i to matrix iv can be carried out in this way. figure 19 illustrates two particular octets ( and ) being switched through the sbs-nse- sbs time:space:time switch.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 158 document id: pmc-2010850, issue 1 figure 28 example graph sbs 0 sbs 1 sbs 2 sbs 3 nse sbs 0 sbs 1 sbs 2 sbs 3 ingress sbss egress sbss figure 29 time:space:time switching in one nse-8g and four single-ported sbss time switching by ingress sbss 0123 0 1 2 3 time space (sbs #) 0123 0 1 2 3 time space (sbs #) 0123 0 1 2 3 time space (sbs #) 0123 0 1 2 3 time space (sbs #) | | time switching by egress sbss space switching by nse (s=1, t=2) => sbs => (s=1, t=0) => nse => (s=0, t=0) => sbs => (s=0, t=3) : : : : : : : : (s=3, t=2) => sbs => (s=3, t=3) => nse => (s=1, t=3) => sbs => (s=1, t=0) i ii iii iv
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 159 document id: pmc-2010850, issue 1 consider a request to route an octet from ingress port i to egress port j, where i and j range from 0 to 3, over four ports corresponding to the four sbs devices. to make this connection, we must find a timeslot in the nse-8g which can accept an octet from the ingress sbs and send an octet to the egress sbs. if the nse-8g has these two slots free in the same timeslot, then the sbss must also have the corresponding slot free. the actual routing of the sample is accomplished in several steps. the octet is: 1. mapped to the free timeslot by the ingress sbs port, 2. picked up by the nse-8g in that timeslot on the port from the ingress sbs and mapped to the port which leads to the egress sbs, 3. picked up by the egress sbs in the expected timeslot. it may not be possible to find a free time which connects the ingress sbs to the egress sbs, even though both sbs devices have unused capacity into the nse-8g core (the ingress sbs may have a free timeslot at time i and the egress sbs may have a free timeslot at time j, but i ~= j). such cases require a more complex algorithm which is capable of disconnecting and reconnecting other connections to make space for the new i to j connection. (disconnection and reconnection of other connections is done hitlessly by nse/sbs fabrics.) this more sophisticated algorithm is described in the remainder of this section. 12.13.3 bi-partite graphs a general solution to the connection problem is a schedule where each connection is assigned to one of the 9720 timeslots in each time stage such that no two connections conflict. this solution then maps to physical switch settings for the sbs and nse-8g devices. the following definitions allow us to represent the problem as an abstract graph problem: 1. draw a graph where each input and output port is represented as a node . 2. partition the graph so that all of the input ports are in one partition and all the output ports are in the other. 3. draw an edge from an input node to an output node if there is a connection from the corresponding input port to the corresponding output port. this results in a bipartite graph where each node has a maximum degree of 9720 (the total number of possible connections from/to a port). a subset of this problem (6 nodes, 2 timeslots) is illustrated in figure 29. we want to assign the edges (connections) to timeslots such that no coincident edges are assigned to the same timeslot. notice that a solution to the problem consists of a permutation (or partial permutation) mapping of input nodes onto output nodes for each of the timeslots. these permutation mappings correspond to one set of switch settings for the nse- 8g devices.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 160 document id: pmc-2010850, issue 1 figure 30 example graph a b c d e f 1 2 3 4 5 6 inputs outputs 12.13.4 unicast scheduling unicast connections through the nse-8g is a relatively simple problem: given n input ports, n output ports, m time slots and a guarantee that no port is oversubscribed, schedule the transfer of all input slots to output slots. this solution uses the time slot interchange on the sbs chips to schedule the flow of inputs to outputs through the nse-8g fabric with no collisions. unicast connections have a perfect solution. example the algorithm is illustrated using an example with 3 timeslots and 6 input/output nodes. the original configuration is shown in figure 30. the new connection originates at input node f , and terminates at output node 6 . this is edge (f 6) in the bipartite graph.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 161 document id: pmc-2010850, issue 1 figure 31 example problem a b c d e f 1 2 3 4 5 6 a b c d e f 1 2 3 4 5 6 a b c d e f 1 2 3 4 5 6 timeslot 1 timeslot 2 timeslot 3 input node f is available on timeslot 3 and output node 6 is available on timeslot 2. merging these two timeslots and adding the edge (f 6) results in the graph shown in figure 31. in this graph, the edges assigned to timeslot 3 are shown as dotted lines. the edge (f 6) is shown in bold. figure 32 merged graph a b c d e f 1 2 3 4 5 6 there are 3 maximal length paths in the merged graph, (a 2 b 1), (d 5), and (c 4 f 6 e 3). the last path mentioned requires re-labeling. if we start with edge (c 4) and traverse the path, alternately labeling with timeslot 2 and 3, we get the graph in figure 32. the timeslot labeling in this graph replaces timeslots 2 and 3 in the original graph (and schedule).
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 162 document id: pmc-2010850, issue 1 figure 33 relabeled graph a b c d e f 1 2 3 4 5 6 12.13.5 experimental results the performance of pmc-sierra?s open path algorithm has been studied by implementing it in c++ and running extensive random connection tests. tests for nse/sbs applications of this algorithm used a single nse-8g connected to 12 sbss, each carrying a full complement of ds0 connection. many runs were completed in which an initially unloaded switch is presented with a sequence of random call establishment requests up to the point of 100% switching loads. these runs were carried out on a 600 mhz alpha running linux. in all of these runs, no otctet open path search took longer than 10 s, thus supporting up to 100,000 1 ds0 call establishments per second. t1s and other aggregates require the establishment of multiple octet open paths; complete t1s can be established at about 3,700 t1/sec. the reasons for this surprisingly good performance are explained in the separate open path algorithm document. it is our opinion that these rates are sufficiently high that the call establishment algorithm should not be a bottleneck in any application of the nse/sbs, and that this rate is sufficiently high to permit the nse/sbs to be used for pstn call establishment rates (up to 100,000 calls/sec in a switch supporting 96,768 full-duplex calls, with the switching core implemented in 1 nse-8g and 12 sbs chips). 12.13.6 multicast scheduling general multicast connections is an entirely different class of problem. with unrestricted multicast, the underlying architecture is non-blocking up to capacity dictated by the number of slots in a frame, but finding the non-blocking schedule is np-hard. there is no polynomial time running algorithm known to solve this class of problem. there are two approaches to solving the multicast problem: ? heuristic algorithms that have statistical probability of success for simple versions of the problem; (and) ? restricted multicast, where the form of restriction provides a means to solve the scheduling problem. 1 this ignores inband or up to nse limitations.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 163 document id: pmc-2010850, issue 1 the general multicast problem is not considered in this document. see the pmc nse-8g documentation for descriptions of the use of multicast in a protection switching schemes; the same concepts apply to nse/sbs fabrics. 12.14 jtag support the nse-8g supports the ieee boundary scan specification as described in the ieee 1149.1 standards. the test access port (tap) consists of the five standard pins, trstb, tck, tms, tdi and tdo used to control the tap controller and the boundary scan registers. the trstb input is the active-low reset signal used to reset the tap controller. tck is the test clock used to sample data on input, tdi and to output data on output, tdo. the tms input is used to direct the tap controller through its states. the basic boundary scan architecture is shown below. figure 34 boundary scan architecture boundary scan register control tdi tdo device identification register bypass register instruction register and decode trstb tms tck test access port controller mux dff select tri-state enable the boundary scan architecture consists of a tap controller, an instruction-register with instruction-decode, a bypass register, a device identification register and a boundary scan register. the tap controller interprets the tms input and generates control signals to load the instruction and data registers. the instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. the bypass register offers a single-bit delay from primary input, tdi to primary output, tdo. the device identification register contains the device identification code. the boundary scan register allows testing of board inter-connectivity. the boundary scan register consists of a shift register place in series with device inputs and outputs. using the boundary scan register, all digital inputs can be sampled and shifted out on primary output, tdo. in addition, patterns can be shifted in on primary input, tdi and forced onto all digital outputs.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 164 document id: pmc-2010850, issue 1 12.14.1 tap controller the tap controller is a synchronous finite state machine clocked by the rising edge of primary input, tck. all state transitions are controlled using primary input, tms. the finite state machine is described below. figure 35 tap controller finite state machine test-logic-reset run-test-idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir trstb=0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 all transitions dependent on input tms 0 0 0 0 0 1 12.14.2 states test-logic-reset the test logic reset state is used to disable the tap logic when the device is in normal mode operation. the state is entered asynchronously by asserting input, trstb. the state is entered synchronously regardless of the current tap controller state by forcing input, tms high for 5 tck clock cycles. while in this state, the instruction register is set to the idcode instruction.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 165 document id: pmc-2010850, issue 1 run-test-idle the run test/idle state is used to execute tests. capture-dr the capture data register state is used to load parallel data into the test data registers selected by the current instruction. if the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. loading occurs on the rising edge of tck. shift-dr the shift data register state is used to shift the selected test data registers by one stage. shifting is from msb to lsb and occurs on the rising edge of tck. update-dr the update data register state is used to load a test register's parallel output latch. in general, the output latches are used to control the device. for example, for the extest instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. the parallel output latches are updated on the falling edge of tck. capture-ir the capture instruction register state is used to load the instruction register with a fixed instruction. the load occurs on the rising edge of tck. shift-ir the shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. shifting is from msb to lsb and occurs on the rising edge of tck. update-ir the update instruction register state is used to load a new instruction into the instruction register. the new instruction must be scanned in using the shift-ir state. the load occurs on the falling edge of tck. the pause-dr and pause-ir states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 166 document id: pmc-2010850, issue 1 boundary scan instructions the following is a description of the standard instructions. each instruction selects a serial test data register path between input, tdi and output, tdo. 12.14.3 instructions bypass the bypass instruction shifts data from input, tdi to output, tdo with one tck clock period delay. the instruction is used to bypass the device. extest the external test instruction allows testing of the interconnection to other devices. when the current instruction is the extest instruction, the boundary scan register is place between input, tdi and output, tdo. primary device inputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. primary device outputs can be controlled by loading patterns shifted in through input tdi into the boundary scan register using the update-dr state. sample the sample instruction samples all the device inputs and outputs. for this instruction, the boundary scan register is placed between tdi and tdo. primary device inputs and outputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. idcode the identification instruction is used to connect the identification register between tdi and tdo. the device's identification code can then be shifted out using the shift-dr state. stctest the single transport chain instruction is used to test out the tap controller and the boundary scan register during production test. when this instruction is the current instruction, the boundary scan register is connected between tdi and tdo. during the capture-dr state, the device identification code is loaded into the boundary scan register. the code can then be shifted out output, tdo using the shift-dr state.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 167 document id: pmc-2010850, issue 1 13 functional timing 13.1 receive interface timing figure 35 below, shows the relative timing of the receive interface. the lvds links carry sonet/sdh frame octets that are encoded in 8b/10b characters. frame boundaries, justification events and alarm conditions are encoded in special control characters. the upstream devices sourcing the links share a common clock and have a common transport frame alignment that is synchronized by the receive serial interface frame pulse signal (rc1fp). due to phase noise of clock multiplication circuits and backplane routing or cable length discrepancies, the links will not phase aligned to each other but are frequency locked. the delay from rc1fp being sampled high to the first and last c1 character is shown in figure 35 in this example, the first c1 is delivered on link rn[x]/rp[x]. the delay to the last c1 represents the time when the all the links have delivered their c1 character. in the example below, link rn[y]/rp[y] is shown to be the slowest. the minimum value for the internal programmable delay (rc1dly[13:0]) is the delay through the sbs 2 plus 15. the maximum value is the delay through the sbs plus 31. consequently, the external system must ensure that the relative delays between all the receive lvds links be less than 16 bytes. the relative phases of the links in figure 35 are shown for illustrative purposes only. links may have different delays relative to other links than what is shown. figure 36 receive interface timing rp[ x ]/ rn[ x ] rn[ y ]/ rp[ y ] ... sysclk rc1fp s4,3/ a2 s1,1/ c1 s2,1/ z0 s4,3/ a2 s1,1/ c1 s2,1/ z0 rc1dly[13:0] delay ... ... ... ... ... max delay between first and last j0s max delay until internal frame pulse ... ... ... min delay until internal frame pulse 2 this delay will be either one frame (9720 clock cycles) or one row (1080 clock cycles) depending on the mode employed.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 168 document id: pmc-2010850, issue 1 13.2 transmit interface timing figure 36 below shows the delay from assertion of rc1fp to the transmit serial data links. due to the presence of fifos in the data path, the delay to the various links can differ by up to eight cycles. the minimum delay (rc1dly + 43 sysclk cycles) is shown to be incurred by one of the transmit protect serial data links (tp[x]/tn[x]). the maximum delay (rc1dly + 51 cycles) is shown to be incurred by one of the transmit auxiliary serial data links (tp[y]/tn[y]). the suggested setting for tc1dly results in a tc1fp pulse at the time at which all the transmit serial links have transmitted their respective c1 characters. the maximum delay from rc1fp to the transmission of a c1 pulse is rc1dly + 52 cycles. therefore the suggested setting for tc1dly is rc1dly+ 52. figure 36 shows the timing of tc1fp with the suggested setting for tc1dly. the relative phases of the links in figure 36 are shown for illustrative purposes only. links may have different delays than what is shown. figure 37 transmit interface timing tp[ x ]/ tn[ x ] tn[ y ]/ tp[ y ] ... sysclk rc1fp s4,3/ a2 s1,1/j0 s2,1/ z0 s4,3/ a2 s1,1/ c1 s2,1/ z0 rc1dly+ max delay(51 cycles) to last c1 ... ... rc1dly + min delay(43 cycles) to first c1 ... ... ... ... tc1fp ... tc1dly (rc1dly + delay to tc1fp(52 cycles)) figure 37 below shows the delay from cmp to the transmit serial data links. cmp is valid only at the rc1fp pulse time, whether rc1fp is pulsed or not. it is ignored at other locations in the transport frame. a change in value to the connection memory page signal (cmp) results in changing the active switch settings. given that cmp is sampled on the rc1fp pulse time, the first data that is switched according to the newly selected connection memory page are the first a1 bytes of the frame following the c1 bytes transmitted by the nse-8g before offset rc1dly + 52 cycles. in more absolute terms, the first a1s transmitted by the nse-8g between offset rc1dly + 43 + 9696 cycles and rc1dly + 51 + 9696 cycles, represent the first data switched according the connection memory page selected by cmp at the rc1fp pulse time.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 169 document id: pmc-2010850, issue 1 figure 38 cmp timing tp[ x ]/ tn[ x ] ... sysclk rc1fp s4,3/ a2 s1,1/ c1 s2,1/ z0 ... valid cmp valid x x rj0dly + delay (43 to 51 cycles) to j0 s1,1/ a1 s2,1/ a1 ... ... ... ... s3,1/ a1 delay to a1: 9696 cycles note: rc1fp may not occur every frame ? it may occur every 1, 4 or 48 frames. rc1fp synchronizes a 9720 count flywheel counter. the terminal count of this counter is used as an internal substitute for rc1fp. in this way the cmp signal is always sampled at the c1 position regardless of the rc1fp presence or absence at the c1 position.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 170 document id: pmc-2010850, issue 1 14 absolute maximum ratings maximum rating are the worst case limits that the device can withstand without sustaining permanent damage. they are not indicative of normal mode operation conditions. table 15 absolute maximum ratings ambient temperature under bias -40c to +85c storage temperature -40c to +125c 1.8v supply voltage (vddi, avdl) -0.3v to +4.6v 3.3v supply voltage (vddo, avdh, csu_avdh) -0.3 to +4.6v input pad tolerance -2v < vddo < +2v for 10ns, 100ma max output pad overshoot limits -2v < vddo < +2v for 10ns, 20ma max voltage on any digital pin -0.3v to vddo+0.3v voltage on lvds pin -0.3 v to avdh + 0.3v static discharge voltage 1000 v latch-up current on rn[i], rp[i], tn[i], tp[i] pins 90 ma latch-up current on resk pin 50 ma latch-up current 100 ma except rn[i], rp[i], tn[i], tp[i], and resk dc input current 20 ma lead temperature +300c absolute maximum junction temperature +150c notes on power supplies 1. when powering up the nse, the following power supply sequence should be observed vddo, avdh, csu_avdh vddi, avdl powering down should be the reverse.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 171 document id: pmc-2010850, issue 1 15 d.c. characteristics t a = -40c to +85c, v ddo 3.3 v 5%, v ddi =1.8 v 5% (typical conditions: t c = 25c, v ddo = 3.3 v, v ddi = 1.8 v) table 16 d.c characteristics symbol parameter min typ max units conditions vddi power supply at 1.8v 1.66 1.8 1.94 volts vddo power supply at 3.3v 3.14 3.3 3.47 volts v il input low voltage 0 tbd 0.8 volts guaranteed input low voltage. v ih input high voltage 2.0 tbd volts guaranteed input high voltage. v ol output or bi-directional low voltage tbd 0.4 volts guaranteed output low voltage at vdd=2.97v and i ol =maximum rated for pad. v oh output or bi-directional high voltage 2.4 tbd volts guaranteed output high voltage at vdd=2.97v and i oh =maximum rated current for pad. v t+ reset input high voltage 2.2 volts applies to rstb and trstb only. v t- reset input low voltage 0.8 volts applies to rstb and trstb only. v th reset input hysteresis voltage tbd volts applies to rstb and trstb only. i ilpu input low current -200 -50 -4 a v il = gnd. notes 1 and 3. i ihpu input high current -10 0 +10 a v ih = v dd . notes 1 and 3. i il input low current -10 0 +10 a v il = gnd. notes 2 and 3. i ih input high current -10 0 +10 a v ih = v dd . notes 2 and 3. c in input capacitance 5pft a =25c, f = 1 mhz c out output capacitance 5pft a =25c, f = 1 mhz
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 172 document id: pmc-2010850, issue 1 symbol parameter min typ max units conditions c io bi-directional capacitance 5pft a =25c, f = 1 mhz i ddop1 operating current tbd ma v dd = 3.3v, outputs unloaded v icm lvds input common-mode range 02.4v |v idm | lvds input differential sensitivity 100 mv r in lvds differential input impedance 85 100 115 ? v loh lvds output voltage high 1375 1475 mv r load =100 ? 1% v lol lvds output voltage low 925 1025 mv r load =100 ? 1% v odm lvds output differential voltage 300 350 400 mv r load =100 ? 1% v ocm lvds output common-mode voltage 1125 1200 1275 mv r load =100 ? 1% r o lvds output impedance, differential 85 110 115 ? |v odm | change in |v odm | between ?0? and ?1? 25 mv r load =100 ? 1% v ocm change in v ocm between ?0? and ?1? 25 mv r load =100 ? 1% i sp , i sn lvds short-circuit output current 10 ma drivers shorted to ground i spn lvds short-circuit output current 10 ma drivers shorted together notes on d.c. characteristics: 1. input pin or bi-directional pin with internal pull-up resistor. 2. input pin or bi-directional pin without internal pull-up resistor 3. negative currents flow into the device (sinking), positive currents flow out of the device (sourcing).
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 173 document id: pmc-2010850, issue 1 16 microprocessor interface timing characteristics (t c = -40c to +85c, v ddo = 3.3v 5%) table 17 microprocessor interface read access symbol parameter min max units ts ar address to valid read set-up time 10 ns th ar address to valid read hold time 5 ns ts alr address to latch set-up time 10 ns th alr address to latch hold time 10 ns tv l valid latch pulse width 5 ns ts lr latch to read set-up 0 ns th lr latch to read hold 5 ns tp rd valid read to valid data propagation delay 30 ns tz rd valid read negated to output tri-state 20 ns tz inth valid read negated to intb high 50 ns figure 39 microprocessor interface read timing valid tzrd tprd tzinth thlr tslr thalr tvl tsalr tvl thar tsar a [11:0] a le c sb+rdb) intb d[31:0] notes on microprocessor interface read timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 v point of the reference signal to the 1.4 v point of the output.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 174 document id: pmc-2010850, issue 1 2. maximum output propagation delays are measured with a 100 pf load on the microprocessor interface data bus, (d[15:0]). 3. a valid read cycle is defined as a logical or of the csb and the rdb signals. 4. in non-multiplexed address/data bus architectures, ale should be held high so parameters ts alr , th alr , tv l , ts lr , and th lr are not applicable. 5. parameter th ar is not applicable if address latching is used. 6. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 v point of the input to the 1.4 v point of the clock. 7. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 v point of the input to the 1.4 v point of the clock.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 175 document id: pmc-2010850, issue 1 table 18 microprocessor interface write access symbol parameter min max units ts aw address to valid write set-up time 10 ns ts dw data to valid write set-up time 20 ns ts alw address to latch set-up time 10 ns th alw address to latch hold time 10 ns tv l valid latch pulse width 5 ns ts lw latch to write set-up 0 ns th lw latch to write hold 5 ns th dw data to valid write hold time 5 ns th aw address to valid write hold time 5 ns tv wr valid write pulse width 40 ns figure 40 microprocessor interface write timing valid thdw tsdw tvwr tvwr tslw thalw tvl tsalw tvl thaw tsaw a [11:0] a le csb+wrb) d[31:0] notes on microprocessor interface write timing: 1. a valid write cycle is defined as a logical or of the csb and the wrb signals. 2. in non-multiplexed address/data bus architectures, ale should be held high so parameters ts alw , th alw , tv l , ts lw , and th lw are not applicable. 3. parameter th aw is not applicable if address latching is used. 4. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 v point of the input to the 1.4 v point of the clock. 5. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 v point of the input to the 1.4 v point of the clock.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 176 document id: pmc-2010850, issue 1 17 a.c. timing characteristics (t a = -40c to +85c, v ddo = 3.3 v 5%, v ddi = 1.8 v 5%) 17.1 input timing table 19 nse-8g input timing (figure 40) symbol description min max units f sysclk sysclk frequency (nominally 77.76 mhz ) -50 +50 ppm thi sysclk sysclk high pulse width 5 ns tlo sysclk sysclk low pulse width 5 ns ts cmp cmp set-up time 3 ns th cmp cmp hold time 0 ns ts rc1 rc1fp set-up time 3 ns th rc1 rc1fp hold time 0 ns figure 41 nse-8g input timing sysclk rc1fp ts rc1 th rc1 cmp ts cmp th cmp tlo sysclk notes on input timing: 1. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 v point of the input to the 1.4 v point of the clock. 2. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 v point of the clock to the 1.4 v point of the input.
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 177 document id: pmc-2010850, issue 1 1.1 reset timing table 20 rstb timing (figure 41 ) symbol description min max units tv rstb rstb pulse width 100 ns figure 42 rstb timing rstb tv rstb
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 178 document id: pmc-2010850, issue 1 17.2 serial sbi bus interface table 21 serial sbi bus interface symbol description min typical max units f rlvds rp[11:0], rn[11:0] bit rate 10f sysclk -100ppm 10f sysclk 10f sysclk + 100ppm mb/s t fall v odm fall time, 80%-20%, (r load =100 ? 1%) 200 300 400 ps t rise v odm rise time, 20%-80%, (r load =100 ? 1%) 200 300 400 ps t skew differential skew 50 ps 17.3 jtag port interface table 22 jtag port interface ( figure 42) symbol description min max units f tck tck frequency 4 mhz thi tck tck hi pulse width 100 ns thi tck tck lo pulse width 100 ns ts tms tms set-up time to tck 25 ns th tms tms hold time to tck 25 ns ts tdi tdi set-up time to tck 25 ns th tdi tdi hold time to tck 25 ns tp tdo tck low to tdo valid 2 25 ns tv trstb trstb pulse width 100 ns
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 179 document id: pmc-2010850, issue 1 figure 43 jtag port interface timing tlotck tlotck thitck thitck tvtrstb tvtrstb tptdo thtms tstms thtdi tstdi tck tdi tms tdo trstb
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 180 document id: pmc-2010850, issue 1 18 ordering and thermal information 18.1 packaging information part no. description PM8621-biap 480 uni ball grid array (ubga) package 18.2 thermal information in full operation (10?12 ports), the nse-8g is designed to operate over a wide temperature range when used with a heat sink with a worst case junction to case tj (tjc) of 1 c/w and is suited for industrial applications such as outside plant equipment maximum long-term operating junction temperature to ensure adequate long-term life 105 0 c maximum junction temperature for short-term excursions with guaranteed continued functional performance. 1 this condition will typically be reached when local ambient reaches 70 deg c. 125 0 c minimum ambient temperature -40 0 c device compact model 2 jc ( 0 c/w) # 1 jb ( 0 c/w) # 4 operating power is dissipated in package (watts) at worst case power supply power (watts) 2.56 sa and cs required for long- term operation 3 sa + cs ( 0 c/w) 4 #5 notes 1. short-term is understood as the definition stated in telcordia generic requirements gr-63-core 2. jc, the junction-to-case thermal resistance is a measured nominal value + 2 sigma. jb , the junction- to-board thermal resistance is obtained by simulating conditions described in jedec standard, jesd 51 3. sa is the thermal resistance of the heat sink to ambient. cs is the thermal resistance of the heat sink attached material 4. the actual sa required may vary according to the air speed at the location of the device in the system with all the components in place device compact model sa cs jc jb ambient heat sink case junction board
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 181 document id: pmc-2010850, issue 1 junction board ambient device compact model jt jb in partial operation (less than 10 ports), this product is designed to operate over a wide temperature range and is suited for industrial applications such as outside plant equipment. maximum long-term operating junction temperature to ensure adequate long-term life 105 0 c maximum junction temperature for short-term excursions with guaranteed continued functional performance 1 this condition will typically be reached when local ambient reaches 85 deg c. 125 0 c minimum ambient temperature -40 0 c thermal resistance vs air flow 2 airflow natural convection 200 lfm 400 lfm ja ( 0 c/w) 13.5 12.2 11.8 device compact model 3 jt ( 0 c/w) # 1 jb ( 0 c/w) # 4 operating power is dissipated in package (watts) at worst case power supply power (watts) 2.56 notes 1. short-term is understood as the definition stated in telcordia generic requirements gr-63-core 2. ja , the total junction to ambient thermal resistance as measured according to jedec standard jesd51 (2s2p) 3. jb , the junction-to-board thermal resistance and jt, the residual junction to ambient thermal resistance are obtained by simulating conditions described in jedec standard, jesd 15-8
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 182 document id: pmc-2010850, issue 1 19 mechanical information the nse-8g is packaged in a 480 ubga package. 480 pin ubga ?35 mm x 35 mm body - (b suffix) b m eee f f f c cab m 20 18 16 14 12 10 8 6 4 2 22 24 26 28 32 34 30 19 17 15 13 11 9 753 21 23 25 27 29 31 33 1 bottom view e a c e g j l n r u w aa ac ae aj al ag an b d f h k m p t v y ab ad af ak ah am ap e1,n a1 ball corner e s s a 2 a a 1 seating plane c bbb c ddd c side view a1 ball corner a1 ball id ink mark d a e b aaa 4x top view package type : 480 thermally enhanced ball grid array - ubga dim. a a 1 a 2 d d 1 ee 1 b aaa bbb min. 0.40 0.92 0.50 nom. 0.50 0.97 35.00 33.00 35.00 33.00 0.63 max. 0.60 1.02 0.70 0.20 0.25 e - - 1.00 1.32 1.47 1.62 ddd - - - - m,n 34x34 body size : 35 x 35 x 1.47 mm - - - - - - 0.20 eee - - 0.30 f f f - - 0.10 - - - - - - s - - 0.05 bsc bsc bsc bsc bsc notes: 1) all dimensions in millimeter. 2) dimension aaa denotes package body profile. 3) dimension bbb denotes parallel. 4) dimension ccc denotes flatness. 5) dimension ddd denotes coplanarity. 6) diameter of solder mask opening is 0.45 +/- 0.025 mm (smd).
nse-8g? standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 183 document id: pmc-2010850, issue 1 notes

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